Miloš Bečvář
ABSTRACT
HDLDLX is a graphically described VHDL model of 5-stage integer pipeline of well known DLX processor. It can be used as a platform explaining logic-level implementation of pipelined processor as a complement to SW functional simulators. Students can interact with model by implementing hazard resolution logic or modifying the pipeline structure. Even though that the model is internally represented in VHDL, the previous knowledge of this language is not required. HDLDLX can be used in conjunction with HDL Designer and Modelsim tools from Mentor Graphics corporation. Article also discusses pros and cons of using commercial EDA tools in undergraduate computer architecture course.
- Patterson, D., Hennessy, J., Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers 1996, 2nd edition Google Scholar
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- Patterson, D., Hennessy, J., Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers 2002, 3rd edition Google ScholarDigital Library
- Yurcik, W., Wolffe, G., Holliday, M., A Survey of Simulators Used in Computer Organization/Architecture Courses, In: Proc. of the 2001 Summer Computer Simulation Conference (SCS 2001), Orlando, USAGoogle Scholar
- Zhang, Y., Adams, G. B.: An Interactive Visual Simulator for DLX pipeline, Newsletter of IEEE Computer Society Technical Cometee on Computer Architecture, September 1997 Google ScholarDigital Library
- Gruenbacher, H., Khosravipour, M., WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture, In: Proc. of IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96) Friedrichshafen, 1996, GERMANY Google ScholarDigital Library
- http://www.computing.dcu.ie/~mike/winmips64.htmlGoogle Scholar
- Brorson, M., MipsIT -- a Simulator and Development Environment using Animation for Computer Architecture Education, In: Proc. of Workshop of Computer Architecture Education, Anchorage, USA, 2002 Google ScholarDigital Library
- ASIP Meister. http://www.eda-meister.orgGoogle Scholar
- Teaching basics of instruction pipelining with HDLDLX
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