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ADAPTS: A digital transient simulation strategy for integrated circuits
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th conference on ACM/IEEE design automation table of contents
San Francisco, California, United States
Pages: 26 - 31  
Year of Publication: 1991
ISBN:0-89791-395-7
Authors
Alexander D. Stein  Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
Tuyen V. Nguyen  Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
Binay J. George  Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
Ronald A. Rohrer  Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Citation Count: 5
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
B.R. Chawla, H.K. Gummel, and P. Kozak. "MOTIS -An MOS timing simulator," IEEE Trans. on Circuits and Systems, CAS-22(12):901-910, December 1975.
 
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Norman P. Jouppi. "Timing Analysis and Performance Improvement of MOS VLSI Designs," IEEE Trans. Computer-Aided Design, CAD-6(4):650-665, July 1987.
 
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Y. H. Kim, J. E. Kleckner, R. A. Saleh, and A. R. Newton. "Electrical-logic simulation," IEEE Int. Conf. on CAD, pages 7-10, 1984.
 
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E. S. Kuh and R. A. Rohrer. "The state variable approach to network analysis," Proc. IEEE, 53:672-686, July 1965.
 
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L. W. Nagel. "SPICE2, a computer program to simulate semiconductor circuits," Technical Report Memo UCB/ERL M520, University of California, Berkeley, May 1975.
 
8
J.K. Ousterhout. "CRYSTAL: A Timing Analyzer for NMOS VLSI Circuits." In Proc. o.f the 3rd Caltech Conference on VLSI, March 1983, pages 57-69.
 
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G. Ruan and J. Vlach. "Current limited switch-level timing simulator for MOS logic networks," Proc. IEEE International Conference on Computer Design, pages 597-601, 1985.
 
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13
C. Visweswariah and R. A. Rohrer. "SPECS2: An integrated circuit timing simulator." In IEEE Int. Conf. on CAD, November 1{}8'/, pages 94-9"/.
 
14
C. Visweswariah and R. A. Rohrer. "Piecewise approximate circuit simulation." In IEEE Int. Conf. on CAD, November 1989, pages 248-251.


Collaborative Colleagues:
Alexander D. Stein: colleagues
Tuyen V. Nguyen: colleagues
Binay J. George: colleagues
Ronald A. Rohrer: colleagues

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