- 1.S. L Hakimi, "Optimum locations of switching cemers and the absolute centers and medians of a graph," Oper. Res., 12, pp. 450-459, 1964.Google ScholarDigital Library
- 2.A. Aho and S. Johnson, "Optimal code generation for expression trees," J. ACM, pp. 488-501,July 1976. Google ScholarDigital Library
- 3.F. R. K. Chung and F. K. Hwang, "The largest minimal rectilinear Steiner trees for a set of n points enclosed in a rectangle with given perimeter," Networks, vol 9, pp. 19-36, 1979.Google ScholarCross Ref
- 4.K.C. Saraswat and F. Mohammadi, "Effect of scaling of interconnections on the time delay of VLSI circuits," IEEE Trans. on Electron Devices, vol ED-29, pp. 645-650, 1982.Google ScholarCross Ref
- 5.Jim Reed, "YACR: Yet Another Channel Router," Master's Report, University of California, Berkeley, February 1985.Google Scholar
- 6.C. Sechen and A. Sangiovanni-Vincentelli, "The TimberWolf placement and routing package,"IEEE J. of Solid State Ch'cuits, vo120, no. 2, pp. 510-522, April 1985.Google ScholarCross Ref
- 7.M. Burstein and M. N. Youssef, "Timing influenced layout design," Proc. 22-nd Design Automation Conference, pp. 124-130, 1985. Google ScholarDigital Library
- 8.K. Keutzer, "DAGON: technology binding and local optimization by DAG matching,"Proc. 24-th Design Automation Conference, pp. 341- 347, 1987. Google ScholarDigital Library
- 9.E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli and A. Wang, "Technology mapping in MIS," Proc. Int. Conf. CAD (ICCAD- 87), pp. 116-119,Nov. 1987.Google Scholar
- 10.R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "MIS: Multiple-level interactive logic optimization system," IEEE Trans. on CAD, vol 6, no. 6, pp. 1062-1081, Nov. 1987.Google ScholarDigital Library
- 11.G. Hachtel, M. Lightner, R. Jacoby, C. Morrison, P. Moceyunas, and D. Bostick, "Bold: The boulder optimal logic design system," in Hawaii Int. Syrup. on Systems Sciences, 1988.Google Scholar
- 12.D.V. Heinbuch ed., CMOS 3 Cell Library, Addison-WesleyPublishing Company, 1988.Google Scholar
- 13.Y.A. EI-Mansy and W. M. Siu, "MOS technology advances," in Handbook of Advanced Semiconductor Technology and Computer Systems, G. Rabbat ed., Van Nostrand Reinhold Company, pp. 229-259, 1988.Google Scholar
- 14.R.S. Tsay, E. S. Kuh, and C.P. Hsu, "PROUD: A sea-of-gates placement algorithm," IEEE Design and Test of Computers, pp. 318-323, Dec. 1988. Google ScholarDigital Library
- 15.M. Pedram and B. T. Preas, "Interconnection length estimation for optimized standard cell layouts," Proc. Int. Conf. CAD (ICCAD-89), pp. 390-393, 1989.Google Scholar
- 16.R. K. Brayton, G. D. Hachtel and A. L. Sangiovanni-Vincenntelli, "Multilevel logic synthesis," Proc. of the IEEE, vo178, no. 2, pp. 264- 300, February 1990.Google ScholarCross Ref
- 17.H.J. Touati, C. W. Moon, R. K. Brayton and A. Wang, "Performanceoriented technology mapping," Proc. 6-th MIT Conf, Advanced Research in VLSI, W. J. Dally ed., pp. 79-97, 1990. Google ScholarDigital Library
- 18.P. Abouzeid, K. Sakouti, G. Saucier and F. Poirot, "Multilevel synthesis minimizing the routing factor," Proc. 27-th Design Automation Conference, pp. 365-368, 1990. Google ScholarDigital Library
- 19.M. Pedram, M. Marek-Sadowska and E. S. Kuh, "Floorplanning with pin assignment," Proc.lnt. Conf. CAD (ICCAD-90), pp. 98-101,1990.Google Scholar
- 20.M. Pedram, N. Bhat and K. Choudhary, "LILY: A layout-driven approach to technology mapping," UCB ERL Memo, Electronics ResearchLaboratory, Univeristy of California, Berkeley., M90/97,1990.Google Scholar
- 21.J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, "GOR- DIAN: VLSI placement by quadratic programming and slicing optimization," IEEE Trans. on CAD, vol 10, no. 3, pp. 356-365, March 1991.Google ScholarDigital Library
Index Terms
- Layout driven technology mapping
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