Probabilistic CTSS

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Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th conference on ACM/IEEE design automation table of contents

San Francisco, California, United States

Pages: 650 - 655

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Yutaka Deguchi	Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan
Nagisa Ishiura	Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan
Shuzo Yajima	Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. A. Breuer and A. D. Friedman: Diagnosis & Reliable Design of Digital Systems, Computer Science Press (1976).
	2	T. Yoneda, K. Nakade and Y. Tohma: A Fast Timing Verification Method Based on the Independence of Units Proc. FTCS-19, pp. 134-141 (1989).
	3	N. Ishiura , M. Takahashi , S. Yajima, Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits, Proceedings of the 26th ACM/IEEE conference on Design automation, p.497-502, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74465]
	4	E. Cerny, P. Rioux and C. Berthet: Comparison of Specification and Implementation for Asynchronous Circuits with Arbitrary Delays, Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pp. 704-720 (1989).
	5	Shin-ichi Minato , Nagisa Ishiura , Shuzo Yajima, Shared binary decision diagram with attributed edges for efficient Boolean function manipulation, Proceedings of the 27th ACM/IEEE conference on Design automation, p.52-57, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123225]
	6	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	7	Nagisa Ishiura , Yutaka Deguchi , Shuzo Yajima, Coded time-symbolic simulation using shared binary decision diagram, Proceedings of the 27th ACM/IEEE conference on Design automation, p.130-135, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123240]
	8	N. Ishiura: Studies on Logic Simulation and Hardware Description Languages, Doctoral Dissertation, Chapter 5, pp. 99-124, Department of Information Science, Kyoto University (1990).

CITED BY 2

	Aseem Agarwal , David Blaauw , Vladimir Zolotov, Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.900, November 09-13, 2003
	Randal E. Bryant, Symbolic Boolean manipulation with ordered binary-decision diagrams, ACM Computing Surveys (CSUR), v.24 n.3, p.293-318, Sept. 1992