ABSTRACT
Off-chip decoupling capacitor (decap) allocation is a demanding task during package and chip codesign. Existing approaches can not handle large numbers of I/O counts and large numbers of legal decap positions. In this paper, we propose a fast decoupling capacitor allocation method. By applying a spectral clustering, a small amount of principal I/Os can be found. Accordingly, the large power supply network is partitioned into several blocks each with only one principal I/O. This enables a localized macromodeling for each block by a triangular-structured reduction. In addition, to systemically consider a large legal position map in a manageable fashion, the map of legal positions is decomposed into multiple rings, which are further parameterized in each block. The decaps are then allocated according to the sensitivity obtained from the parameterized macro-model for each block. Compared to the PRIMA-based macromodeling, experiments show that our method (TBS2) is 25X faster and has 3.04X smaller error. Moreover, our decap allocation reduces the optimization time by 97X, and reduces decap cost by up to 16% to meet the same power-integrty target.
- H. Zheng and et. al., "On-package decoupling optimization with package macromodels," in Proc. CICC, 2003.Google Scholar
- J. Chen and et. al., "Noise-driven in-package decoupling capacitance insertion," in Proc. ISPD, 2006. Google ScholarDigital Library
- S. Pant and et. al., "Power grid physics and implications for CAD," in Proc. DAC, 2006. Google ScholarDigital Library
- H. Yu and et. al., "A fast block structure preserving model order reduction for inverse inductance circuits," in Proc. ICCAD, 2006. Google ScholarDigital Library
- P. Feldmann and et. al., "Sparse and efficient reduced order modeling of linear sub-circuits with large number of terminals," in Proc. ICCAD, 2004. Google ScholarDigital Library
- P. Liu and et. al., "Efficient method for terminal reduction of interconnect circuits considering delay variations," in Proc. ICCAD, 2005. Google ScholarDigital Library
- C. Ding, "Spectral clustering, principal component analysis and matrix factorizations for learning," in Int't Conf. on Machine Learning (Tutorial), 2005.Google Scholar
- H. Yu and et. al., "Fast analysis of structured power grid by triangularization based structure preserving model order reduction," in Proc. DAC, 2006. Google ScholarDigital Library
Index Terms
- Off-chip decoupling capacitor allocation for chip package co-design
Recommendations
Effective radii of on-chip decoupling capacitors
Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard ceil circuit blocks. The efficacy of on-...
Fully on-chip switched capacitor NMOS low dropout voltage regulator
This paper presents a 1.5 V 50 mA low dropout voltage (LDO) regulator using an NMOS transistor as the output pass element. Continuous time operation of the LDO is achieved using a new switched floating capacitor scheme that raises the gate voltage of ...
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
SBCCI '03: Proceedings of the 16th symposium on Integrated circuits and systems designThe on-chip decoupling capacitors are widely used in today's high-performance microprocessor design to mitigate the power supply noise problem. The continued reduction of oxide thickness in advanced nanotechnology, however, also significantly increases ...
Comments