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Off-chip decoupling capacitor allocation for chip package co-design

Published:04 June 2007Publication History

ABSTRACT

Off-chip decoupling capacitor (decap) allocation is a demanding task during package and chip codesign. Existing approaches can not handle large numbers of I/O counts and large numbers of legal decap positions. In this paper, we propose a fast decoupling capacitor allocation method. By applying a spectral clustering, a small amount of principal I/Os can be found. Accordingly, the large power supply network is partitioned into several blocks each with only one principal I/O. This enables a localized macromodeling for each block by a triangular-structured reduction. In addition, to systemically consider a large legal position map in a manageable fashion, the map of legal positions is decomposed into multiple rings, which are further parameterized in each block. The decaps are then allocated according to the sensitivity obtained from the parameterized macro-model for each block. Compared to the PRIMA-based macromodeling, experiments show that our method (TBS2) is 25X faster and has 3.04X smaller error. Moreover, our decap allocation reduces the optimization time by 97X, and reduces decap cost by up to 16% to meet the same power-integrty target.

References

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  1. Off-chip decoupling capacitor allocation for chip package co-design

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    • Published in

      cover image ACM Conferences
      DAC '07: Proceedings of the 44th annual Design Automation Conference
      June 2007
      1016 pages
      ISBN:9781595936271
      DOI:10.1145/1278480

      Copyright © 2007 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 4 June 2007

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      DAC '07 Paper Acceptance Rate152of659submissions,23%Overall Acceptance Rate1,770of5,499submissions,32%

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