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Thousand core chips: a technology perspective

Published: 04 June 2007 Publication History

Abstract

This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.

References

[1]
Shekhar Borkar, "Design Challenges of Technology Scaling, IEEE Micro", July-August 1999.
[2]
Tschanz J., et al, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors", IEEE Journal of Solid State Circuits, November 2003.
[3]
Pham D. et al, "The design and implementation of a first-generation CELL processor", ISSCC 2005.
[4]
Vangal et al, "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS", ISSCC 2007.
[5]
Shekhar Borkar et al, "Parameter Variations and Impact on Circuits and Microarchitecture", Proceedings, DAC 2003.
[6]
Shekhar Borkar, "Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation", IEEE Micro, November-December 2005.

Cited By

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  • (2025)Reinforcement learning for thermal and reliability management in manycore systemsDesign Automation for Embedded Systems10.1007/s10617-024-09292-029:1Online publication date: 1-Mar-2025
  • (2024)Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00018(33-38)Online publication date: 1-Jul-2024
  • (2024)Hardware ArchitectureEdge Computing Acceleration10.1002/9781119813873.ch5(125-166)Online publication date: 29-Nov-2024
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    cover image ACM Conferences
    DAC '07: Proceedings of the 44th annual Design Automation Conference
    June 2007
    1016 pages
    ISBN:9781595936271
    DOI:10.1145/1278480
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 04 June 2007

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    Author Tags

    1. CMOS
    2. memory
    3. power
    4. reliability
    5. variability

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    DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;
    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2025)Reinforcement learning for thermal and reliability management in manycore systemsDesign Automation for Embedded Systems10.1007/s10617-024-09292-029:1Online publication date: 1-Mar-2025
    • (2024)Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00018(33-38)Online publication date: 1-Jul-2024
    • (2024)Hardware ArchitectureEdge Computing Acceleration10.1002/9781119813873.ch5(125-166)Online publication date: 29-Nov-2024
    • (2023)Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.331413531:12(1896-1904)Online publication date: 1-Dec-2023
    • (2023)Efficient Parallel Mining of High-utility Itemsets on Multicore Processors2023 IEEE 39th International Conference on Data Engineering (ICDE)10.1109/ICDE55515.2023.00388(638-652)Online publication date: Apr-2023
    • (2023)Fault-Tolerant Network-On-ChipBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design10.1007/978-981-19-8551-5_4(169-241)Online publication date: 2-Mar-2023
    • (2023)Fault-Tolerant General Purposed ProcessorsBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design10.1007/978-981-19-8551-5_3(117-168)Online publication date: 2-Mar-2023
    • (2022)Towards practical multikernel OSes with MySySProceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3546591.3547525(29-37)Online publication date: 23-Aug-2022
    • (2022)Sherman: A Write-Optimized Distributed B+Tree Index on Disaggregated MemoryProceedings of the 2022 International Conference on Management of Data10.1145/3514221.3517824(1033-1048)Online publication date: 10-Jun-2022
    • (2022)WiZ-BMS: A Hybrid Wireless Network-on-Chip Design with Fully Adaptive Routing2022 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES54909.2022.00056(242-247)Online publication date: Dec-2022
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