Rajiv Joshi
ABSTRACT
This paper presents a novel dynamic supply boosting technique for low voltage SRAMs at/beyond 65 nm PD/SOI technologies. For the first time the technique exploits the capacitive coupling effect in a floating-body PD/SOI device to dynamically boost the virtual array supply voltage during Read operation, thus improving the Read performance, Read/half-select stability, and Vmin. This enables significant reduction of the standby cell power and circuit active power in a single supply methodology. The performance and parametric yield improvements in the presence of variability are analyzed/validated using precise and fast Monte Carlo statistical circuit simulations with mixture importance sampling. Fabricated column-based 65nm PD/SOI SRAM circuits are confirmed with simulations and physical analysis and are shown to operate at 0.4 V. to 0.5V.
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Digital Library
- R. V. Joshi et al., "Variability Analysis for Sub-100 nm PD/SOI CMOS SRAM cell", Proc. of the 30th ESSCC, 2004, pp. 211--214.Google Scholar
- R. Joshi et al. "Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell", ESSCIRC 2006.Google ScholarCross Ref
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- R. Kanj et al., "Mixture Importance Sampling and Its Application to the Analysis of SRAM Designs in the Presence of Rare Failure Events", DAC 2006. Google ScholarDigital Library
- M. Yamaoka et al., "90nm Process Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique", IEEE JSSC, Match 2006.Google Scholar
- G. Ming et al., "Low Power SRAM design Using Charge sharing Technique", 6th IEEE ASIC Conf. Oct 2005.Google Scholar
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- L. Chang et al., "Stable Cell Design for the 32nm Node and Beyond", IEEE Symposium on VLSI Technology, 2005.Google Scholar
- Y. Tsividis, Operation and Modeling of the MOS transistor, Prenice-Hall, 1987. Google ScholarDigital Library
Index Terms
- A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies
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