ABSTRACT
In this paper, we present a novel FIR filter synthesis technique that allows aggressive voltage scaling by exploiting the fact that all filter coefficients are not equally important to obtain a "reasonably accurate" filter response. Our technique implements a Level Constrained Common Subexpression Elimination (LCCSE) algorithm, where we can constrain the number of adder levels required to compute each of the coefficient outputs. By specifying a tighter constraint (in terms of number of adders in the critical path) on the important coefficients, we ensure that the later computational steps compute only the less important coefficient outputs. In case of delay variations due to voltage scaling and/or process variations, only the less important outputs are affected, resulting in graceful degradation of filter quality. The proposed architecture, therefore, lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under extreme process variation and supply voltage scaling (0.8V), filters implemented in BPTM 70 nm technology show an average power savings of 25-30% with minor degradation in filter response.
- K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, Wiley, NY 1999.Google Scholar
- R. M. Hewlitt et al., "Canonical signed digit representation for FIR digital filters",SIPS 2001, pp. 416--426.Google Scholar
- C. Yao et al., "A Novel Common-Subexpression-Elimination Method for Synthesizing Fixed-Point FIR Filters" , TCAS-1, vol 51, 2004, pp. 2215--2211.Google Scholar
- Y. Takahashi et al., "New Cost-effective VLSI Impl. of Multiplierless FIR Filter using Common Subexpression Elimination", ISCAS 2005, pp. 1445--1448.Google Scholar
- A. Hosangadi et al., "Algebraic Methods for Optimizing ConstantallMultiplications in Linear Systems", VLSI Signal Processing, March 2006. Google ScholarDigital Library
- S. Borkar et al., "Parameter variations and impact on circuits and micro--architecture", DAC 2003, pp. 338--342. Google ScholarDigital Library
- Synopsys, http://www.synopsys.com.Google Scholar
- Predictive Technology Model, http://www.eas.asu.edu/~ptm/Google Scholar
- Y.C. Lim et al., "Discrete coefficient FIR digital filter design based upon an LMS criteria," IEEE TCAS, volume 30, 1983, pp. 723--739.Google Scholar
- J.G. Proakis et al. "Digital Signal Processing:Principles, Algorithms and Applications", Prentice Hall, NJ, 1996. Google ScholarDigital Library
- C.H. Kim et al., "On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations", Symp. of VLSI Circuits, 2004,pp.250--251.Google ScholarCross Ref
Index Terms
- A process variation aware low power synthesis methodology for fixed-point FIR filters
Recommendations
Variation-aware low-power synthesis methodology for fixed-point FIR filters
In this paper, we present a novel finite-impulse response (FIR) filter synthesis technique that allows for aggressive voltage scaling by exploiting the fact that all filter coefficients are not equally important to obtain a "reasonably accurate" filter ...
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
According to Moore's law, the number of transistors in a chip doubles every 18 months. The increased transistor-count leads to increased power density. Thus, in modern circuits, power efficiency is a central determinant of circuit efficiency. With ...
A power-predictive environment for fast and power-aware ASIC-based FIR filter design
SBCCI '17: Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the SandsNowadays, the amount of small devices performing any kind of Digital Signal Processing (DSP) has increased drastically. On the other hand, the limited energy available to such battery-powered devices is a real problem. In DSP applications, one of the ...
Comments