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Voltage- and ABB-island optimization in high level synthesis

Published: 27 August 2007 Publication History

Abstract

Using our framework supporting simultaneous behavioral to RTL synthesis, component-wise floorplanning, as well as ABB (adaptive body biasing) and VDD aware power and delay prediction, we present a performance neutral methodology for optimal VDD-island generation and multiple ABB application. We show that tuning supply and body voltage for the entire design reduces the total energy dissipation by 4.6-38.1% without any performance loss. By allowing more than one body voltage and without optimizing the floorplan, the savings do not rise any further. Carefully floorplanning the design, we can additionally use VDD-islands reducing the power by 8.7-49.2%. In addition to the power savings, the power and delay variability due to PTV (process, temperature, voltage) variation can be reduced with all proposed ABB approaches, assuming that only the chip structure has to be fixed at design time, but the voltage levels can be adapted after the system manufacturing.

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Ali Keshavarzi, James W. Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins: Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Design and Test of Computers: 2002
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Cited By

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  • (2017)A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation CompensationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E100.A.1439E100.A:7(1439-1451)Online publication date: 2017
  • (2016)A delay variation and floorplan aware high-level synthesis algorithm with body biasing2016 17th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2016.7479179(75-80)Online publication date: Mar-2016
  • (2015)A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structureIntegration, the VLSI Journal10.1016/j.vlsi.2015.05.00451:C(46-60)Online publication date: 1-Sep-2015
  • Show More Cited By

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  1. Voltage- and ABB-island optimization in high level synthesis

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    cover image ACM Conferences
    ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design
    August 2007
    432 pages
    ISBN:9781595937094
    DOI:10.1145/1283780
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 27 August 2007

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    Author Tags

    1. adaptive body biasing
    2. leakage
    3. process variation
    4. voltage islands

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    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    View all
    • (2017)A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation CompensationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E100.A.1439E100.A:7(1439-1451)Online publication date: 2017
    • (2016)A delay variation and floorplan aware high-level synthesis algorithm with body biasing2016 17th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2016.7479179(75-80)Online publication date: Mar-2016
    • (2015)A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structureIntegration, the VLSI Journal10.1016/j.vlsi.2015.05.00451:C(46-60)Online publication date: 1-Sep-2015
    • (2014)Variability-aware architecture level optimization techniques for robust nanoscale chip designComputers and Electrical Engineering10.1016/j.compeleceng.2013.11.02640:1(168-193)Online publication date: 1-Jan-2014
    • (2013)Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply VoltagesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.2597E96.A:12(2597-2611)Online publication date: 2013
    • (2009)Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation predictionProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594243(33-38)Online publication date: 19-Aug-2009
    • (2007)Modelling the impact of high level leakage optimization techniques on the delay of RT-componentsProceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation10.5555/2391795.2391817(171-180)Online publication date: 3-Sep-2007
    • (2007)Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-ComponentsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-74442-9_17(171-180)Online publication date: 2007

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