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A low-power SRAM using bit-line charge-recycling technique

Published: 27 August 2007 Publication History

Abstract

We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13μm CMOS and measurement results show 88% reduction in total power compared to the conventional SRAM (CON-SRAM) at VDD=1.5V and f=100MHz.

References

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Cited By

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  • (2022)Design and Analysis of Two Low Power SRAM Cell Structures2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)10.1109/AISP53593.2022.9760587(1-7)Online publication date: 12-Feb-2022
  • (2017)10T SRAM Using Half- $V_{\text {DD}}$ Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL LeakageIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263791825:4(1193-1203)Online publication date: 1-Apr-2017
  • (2016)In-Memory Computing Architectures for Sparse Distributed MemoryIEEE Transactions on Biomedical Circuits and Systems10.1109/TBCAS.2016.254540210:4(855-863)Online publication date: Aug-2016
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    cover image ACM Conferences
    ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design
    August 2007
    432 pages
    ISBN:9781595937094
    DOI:10.1145/1283780
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 27 August 2007

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    Author Tags

    1. SRAM
    2. charge-recycling
    3. low power
    4. process variation
    5. write margin
    6. write power

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    View all
    • (2022)Design and Analysis of Two Low Power SRAM Cell Structures2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)10.1109/AISP53593.2022.9760587(1-7)Online publication date: 12-Feb-2022
    • (2017)10T SRAM Using Half- $V_{\text {DD}}$ Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL LeakageIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263791825:4(1193-1203)Online publication date: 1-Apr-2017
    • (2016)In-Memory Computing Architectures for Sparse Distributed MemoryIEEE Transactions on Biomedical Circuits and Systems10.1109/TBCAS.2016.254540210:4(855-863)Online publication date: Aug-2016
    • (2010)The application and implementation of face recognition in authentication system for distance education2010 International Conference on Networking and Digital Society10.1109/ICNDS.2010.5479246(487-489)Online publication date: May-2010
    • (2009)Design and analysis of two low-power SRAM cell structuresIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200459017:10(1551-1555)Online publication date: 1-Oct-2009

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