skip to main content
article
Free access

Computing with a trillion crummy components

Published: 01 September 2007 Publication History

Abstract

Attempting to build nanometer-scale circuits that are both defect- and fault-tolerant.

Supplementary Material

PDF File (p35-robinett.jp.pdf)
Requires Asian Language Support in Adobe Reader and Japanese Language Support in Your Browser.

References

[1]
Chakraborty, K. and Mazumder, P. Fault Tolerance and Reliability Techniques for High-Density Random-Access Memories. Prentice Hall, 2002.
[2]
Chen, Y. et al. Nanoscale molecular switch devices fabricated by imprint lithography. Applied Physics Letters 82 (2003), 1610--1612.
[3]
Heath, J.R., Kuekes, P.J., Snider, G.S., and Williams, R.S. A defect-tolerant computer architecture: Opportunities for nanotechnology. Science 280 (1998), 1716.
[4]
Kuekes, P.J., Robinett, W., Seroussi, G., and Williams R.S. Defect-tolerant interconnect to nanoelectronic circuits: Internally-redundant demultiplexers based on error-correcting codes. Nanotechnology 16 (2005), 869.
[5]
Kuekes, P.J. and Williams, R.S. Demultiplexer for a molecular wire crossbar network. U.S. Patent No. 6,256,767 (July 3, 2001).
[6]
Moore, E.F. and Shannon, C.E. Reliable circuits using less reliable relays. Journal of the Franklin Institute (1956), 191--208, 281--297.
[7]
Siewiorek, D.P. and Swarz, D.S. Reliable Computer Systems: Design and Evaluation, 3rd edition. AK Peters, Ltd., 1998.
[8]
Snider, G.S. and Williams, R.S. Nano/CMOS architectures using field-programmable nanowire interconnect. Nanotechnology, 2006.
[9]
Strukov, D.B. and Likharev, K.K. CMOL FPGA: A cell-based, reconfigurable architecture for hybrid digital circuits using two-terminal nanodevices. Nanotechnology; preprint available at rsfq1.physics.sunysb.edu/likharev/nano/FPGA05.pdf.
[10]
Strukov, D.B. and Likharev, K.K. A reconfigurable architecture for hybrid CMOS/nanodevice circuits. In Proceedings of FCCM'05 (Napa Valley, CA, April 2005); preprint available at rsfq1.physics.sunysb.edu/likharev/nano/FCCM2005.pdf.
[11]
Strukov, D.B. and Likharev, K.K. Prospects for terabit-scale nanoelectronics memories. Nanotechnology 16, 137 (2005).
[12]
von Neumann, J. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In C.E. Shannon and J. McCarthy, Eds., Automata Studies (1955), 43--98.

Cited By

View all
  • (2014)An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto NanocrossbarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228275533:1(64-75)Online publication date: 1-Jan-2014
  • (2014)Resilient data encoding for fault-prone signal transmission in parallelized signed-digit based arithmeticPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware10.1007/BF0334202129:1(5-14)Online publication date: 6-Feb-2014
  • (2013)Defect-tolerant logic hardening for crossbar-based nanosystemsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485713(1801-1806)Online publication date: 18-Mar-2013
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image Communications of the ACM
Communications of the ACM  Volume 50, Issue 9
ACM's plan to go online first
September 2007
104 pages
ISSN:0001-0782
EISSN:1557-7317
DOI:10.1145/1284621
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 2007
Published in CACM Volume 50, Issue 9

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)170
  • Downloads (Last 6 weeks)33
Reflects downloads up to 14 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2014)An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto NanocrossbarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228275533:1(64-75)Online publication date: 1-Jan-2014
  • (2014)Resilient data encoding for fault-prone signal transmission in parallelized signed-digit based arithmeticPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware10.1007/BF0334202129:1(5-14)Online publication date: 6-Feb-2014
  • (2013)Defect-tolerant logic hardening for crossbar-based nanosystemsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485713(1801-1806)Online publication date: 18-Mar-2013
  • (2013)Analysis of Memristor Based Circuitsi-manager's Journal on Circuits and Systems10.26634/jcir.1.3.24451:3(23-28)Online publication date: 15-Aug-2013
  • (2013)Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary AlgorithmsIEEE Transactions on Computers10.1109/TC.2013.5862:8(1526-1541)Online publication date: 1-Aug-2013
  • (2012)Selectively fortifying reconfigurable computing device to achieve higher error resilienceJournal of Electrical and Computer Engineering10.1155/2012/5935322012(5-5)Online publication date: 1-Jan-2012
  • (2012)Quantum walksQuantum Information Processing10.1007/s11128-012-0432-511:5(1015-1106)Online publication date: 1-Oct-2012
  • (2011)Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneouslyProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132433(456-462)Online publication date: 7-Nov-2011
  • (2011)Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneouslyProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105368(456-462)Online publication date: 7-Nov-2011
  • (2011)Discriminatively Fortified Computing with Reconfigurable Digital FabricProceedings of the 2011 IEEE 13th International Symposium on High-Assurance Systems Engineering10.1109/HASE.2011.49(112-119)Online publication date: 10-Nov-2011
  • Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Magazine Site

View this article on the magazine site (external)

Magazine Site

Login options

Full Access

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media