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A new efficient retiming algorithm derived by formal manipulation

Published: 06 February 2008 Publication History

Abstract

A new efficient algorithm is derived for the minimal period retiming by formal manipulation. Contrary to all previous algorithms, which used fixed period feasibility checking to binary-search a candidate range, the derived algorithm checks the optimality of a feasible period directly. It is much simpler and more efficient than previous algorithms. Experimental results showed that it is even faster than ASTRA, an efficient heuristic algorithm. Since the derived algorithm is incremental by nature, it also opens the opportunity to be combined with other optimization techniques.

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  • (2013)Retiming for Soft Error Minimization Under Error-Latching Window ConstraintsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485530(1008-1013)Online publication date: 18-Mar-2013
  • (2011)Network flow-based simultaneous retiming and slack budgeting for low power designProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950913(473-478)Online publication date: 25-Jan-2011
  • (2011)Retiming Pulsed-Latch Circuits With Regulating Pulse WidthIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.212693230:8(1114-1127)Online publication date: 1-Aug-2011
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  1. A new efficient retiming algorithm derived by formal manipulation

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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 1
    January 2008
    496 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1297666
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 06 February 2008
    Accepted: 01 April 2007
    Revised: 01 July 2005
    Received: 01 July 2004
    Published in TODAES Volume 13, Issue 1

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    Author Tags

    1. Clockperiod minimization
    2. algorithm derivation
    3. retiming

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    Cited By

    View all
    • (2013)Retiming for Soft Error Minimization Under Error-Latching Window ConstraintsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485530(1008-1013)Online publication date: 18-Mar-2013
    • (2011)Network flow-based simultaneous retiming and slack budgeting for low power designProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950913(473-478)Online publication date: 25-Jan-2011
    • (2011)Retiming Pulsed-Latch Circuits With Regulating Pulse WidthIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.212693230:8(1114-1127)Online publication date: 1-Aug-2011
    • (2011)Network flow-based simultaneous retiming and slack budgeting for low power design16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722236(473-478)Online publication date: Jan-2011
    • (2010)Simultaneous slack budgeting and retiming for synchronous circuits optimizationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899733(49-54)Online publication date: 18-Jan-2010
    • (2010)Multicore parallelization of min-cost flow for CAD applicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206115029:10(1546-1557)Online publication date: 1-Oct-2010
    • (2010)Simultaneous slack budgeting and retiming for synchronous circuits optimization2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419919(49-54)Online publication date: Jan-2010

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