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Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes

Published: 06 February 2008 Publication History

Abstract

As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. In this article, we first propose a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for nonhuge application-specific SoCs. The structure of the crossroad switch is simple, which can be regarded as a NoC-lite router, and we can easily construct a low-power on-chip network with these switches by a system-level design methodology. We also present the design methodology to tailor the proposed interconnection architecture to low-power structures by two proposed optimization schemes with profiled communication characteristics. The first scheme is power-aware topology construction, which can build low-power application-specific interconnection topologies. To further reduce the power consumption, we propose the second optimization scheme to predetermine the operating mode of dual-mode switches in the NoC at runtime. We evaluate several interconnection techniques, and the results show that the proposed architecture is more low-power and high-performance than others under some constraints and scale boundaries. We take multimedia applications as case studies, and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture. The power consumption can be further reduced approximately 25% by applying partially dedicated path mechanism.

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 1
      January 2008
      496 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/1297666
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 06 February 2008
      Accepted: 01 August 2007
      Received: 01 May 2007
      Published in TODAES Volume 13, Issue 1

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      Author Tags

      1. Application specific
      2. interconnection
      3. low power
      4. networks on chip
      5. systems on chips

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      • (2013)An energy-aware online task mapping algorithm in NoC-based systemThe Journal of Supercomputing10.1007/s11227-011-0678-164:3(1021-1037)Online publication date: 1-Jun-2013
      • (2012)Improving performance of multi-core NUCA coherent systems using NoC-assisted mechanismsThe Journal of Supercomputing10.1007/s11227-012-0793-762:3(1318-1337)Online publication date: 9-Jun-2012
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