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Synthesis of a novel timing-error detection architecture

Published: 06 February 2008 Publication History

Abstract

Delay variation can cause a design to fail its timing specification. Ernst et al. [2003] observe that the worst delay of a design is least probable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their experimental results show significant performance (or power) gain as compared with the worst-case design. However, the architecture in Ernst et al. [2003] suffers the short path problem, which is difficult to resolve. In this article, we propose a novel error-detecting architecture to solve the short path problem. Our experimental results show considerable performance gain can be achieved with reasonable area overhead.

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  • (2016)Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation2016 29th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2016.7905508(350-355)Online publication date: Sep-2016
  • (2011)Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770740(1-6)Online publication date: Mar-2011
  • (2010)Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessorsProceedings of the 12th international conference on Formal engineering methods and software engineering10.5555/1939864.1939894(355-370)Online publication date: 17-Nov-2010
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  1. Synthesis of a novel timing-error detection architecture

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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 1
    January 2008
    496 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1297666
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 06 February 2008
    Accepted: 01 July 2007
    Revised: 01 May 2007
    Received: 01 May 2006
    Published in TODAES Volume 13, Issue 1

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    Author Tags

    1. Logic synthesis
    2. fault tolerance

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    View all
    • (2016)Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation2016 29th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2016.7905508(350-355)Online publication date: Sep-2016
    • (2011)Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770740(1-6)Online publication date: Mar-2011
    • (2010)Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessorsProceedings of the 12th international conference on Formal engineering methods and software engineering10.5555/1939864.1939894(355-370)Online publication date: 17-Nov-2010
    • (2010)Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scalingACM Transactions on Design Automation of Electronic Systems10.1145/1698759.169876715:2(1-17)Online publication date: 2-Mar-2010
    • (2010)Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined MicroprocessorsFormal Methods and Software Engineering10.1007/978-3-642-16901-4_24(355-370)Online publication date: 2010
    • (2009)Logic synthesis for better than worst-case designs2009 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2009.5158121(166-169)Online publication date: Apr-2009

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