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Low-power gated and buffered clock network construction

Published: 06 February 2008 Publication History

Abstract

We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given the module locations and activity information. Unlike previous works, we consider masking logic insertion and buffer insertion simultaneously, and guarantee to yield a zero-skew clock tree. Both the logical and physical information of the modules are carefully taken into consideration when determining where masking logic should be inserted. We also account for the power overhead of the control signals so that the total average power consumption of the constructed zero-skew gated clock network can be minimized. To this end, we present a recursive approach to compute the effective switched capacitance of a general gated and buffered clock network, accounting for both the clock tree's and controller tree's switched capacitance. The power consumptions of the gated clock networks constructed by our algorithm are 20 to 36% lower than those reported in the best previous work in the literature.

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  • (2020)Optimal bounded-skew steiner trees to minimize maximum k-active dynamic powerProceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop10.1145/3414622.3431908(1-8)Online publication date: 5-Nov-2020
  • (2018)A SAT-Based Methodology for Effective Clock Gating for Power MinimizationJournal of Circuits, Systems and Computers10.1142/S021812661950011728:01(1950011)Online publication date: 15-Oct-2018
  • (2017)Low-Power Clock Tree Synthesis for 3D-ICsACM Transactions on Design Automation of Electronic Systems10.1145/301961022:3(1-24)Online publication date: 5-Apr-2017
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 1
January 2008
496 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/1297666
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 06 February 2008
Accepted: 01 August 2007
Revised: 01 April 2007
Received: 01 November 2006
Published in TODAES Volume 13, Issue 1

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Author Tags

  1. Clock tree
  2. buffer
  3. clock gating
  4. low power
  5. zero-skew

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Cited By

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  • (2020)Optimal bounded-skew steiner trees to minimize maximum k-active dynamic powerProceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop10.1145/3414622.3431908(1-8)Online publication date: 5-Nov-2020
  • (2018)A SAT-Based Methodology for Effective Clock Gating for Power MinimizationJournal of Circuits, Systems and Computers10.1142/S021812661950011728:01(1950011)Online publication date: 15-Oct-2018
  • (2017)Low-Power Clock Tree Synthesis for 3D-ICsACM Transactions on Design Automation of Electronic Systems10.1145/301961022:3(1-24)Online publication date: 5-Apr-2017
  • (2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
  • (2016)Power-efficient and slew-aware three dimensional gated clock tree synthesis2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2016.7753535(1-6)Online publication date: Sep-2016
  • (2015)Synthesis for Power-Aware Clock SpinesProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840837(126-131)Online publication date: 2-Nov-2015
  • (2015)Synthesis for power-aware clock spines2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2015.7372559(126-131)Online publication date: Nov-2015
  • (2014)Gated low-power clock tree synthesis for 3D-ICsProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627665(319-322)Online publication date: 11-Aug-2014
  • (2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
  • (2013)Low-power anti-aging zero skew clock gatingACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244209818:2(1-37)Online publication date: 11-Apr-2013
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