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Optimizing wirelength and routability by searching alternative packings in floorplanning

Published: 06 February 2008 Publication History

Abstract

Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a smaller interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area.

References

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  1. Optimizing wirelength and routability by searching alternative packings in floorplanning

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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 1
    January 2008
    496 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1297666
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 06 February 2008
    Accepted: 01 July 2007
    Revised: 01 June 2007
    Received: 01 June 2006
    Published in TODAES Volume 13, Issue 1

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    Author Tags

    1. Floorplanning
    2. wirelength reduction

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