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Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip

Authors:

Zhonghai Lu,

Axel JantschAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 18 - 25

Published: 05 November 2007 Publication History

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Abstract

Configuring Time-Division-Multiplexing (TDM) Virtual Circuits (VCs) for network-on-chip must guarantee conflict freedom for overlapping VCs besides allocating sufficient time slots to them. These requirements are fulfilled in the slot allocation phase. In the paper, we define the concept of a logical network (LN). Based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free VCs. Using these theorems, slot allocation for VCs becomes a procedure of computing LNs and then assigning VCs to different LNs. TDM VC configuration can thus be predictable and correct-by-construction. We have integrated this slot allocation method into our multi-node VC configuration program and applied the program to an industrial application.

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Harde TFreier Mvon der Brüggen GChen JOuhammou YRidouard FGrolleau EJan MBehnam M(2018)Configurations and Optimizations of TDMA Schedules for Periodic Packet Communication on Networks on ChipProceedings of the 26th International Conference on Real-Time Networks and Systems10.1145/3273905.3273928(202-212)Online publication date: 10-Oct-2018
https://dl.acm.org/doi/10.1145/3273905.3273928
Hesham SRettkowski JGoehringer DAbd El Ghany M(2017)Survey on Real-Time Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.262361928:5(1500-1517)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TPDS.2016.2623619
Mirza UGruian FKuchcinski K(2014)Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chipComputers and Electrical Engineering10.1016/j.compeleceng.2014.08.01540:8(276-291)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.compeleceng.2014.08.015
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Published In

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Publisher

IEEE Press

Publication History

Published: 05 November 2007

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ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Harde TFreier Mvon der Brüggen GChen JOuhammou YRidouard FGrolleau EJan MBehnam M(2018)Configurations and Optimizations of TDMA Schedules for Periodic Packet Communication on Networks on ChipProceedings of the 26th International Conference on Real-Time Networks and Systems10.1145/3273905.3273928(202-212)Online publication date: 10-Oct-2018
https://dl.acm.org/doi/10.1145/3273905.3273928
Hesham SRettkowski JGoehringer DAbd El Ghany M(2017)Survey on Real-Time Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.262361928:5(1500-1517)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TPDS.2016.2623619
Mirza UGruian FKuchcinski K(2014)Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chipComputers and Electrical Engineering10.1016/j.compeleceng.2014.08.01540:8(276-291)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.compeleceng.2014.08.015
Mirza UGruian FKuchcinski KPalesi MMak TDaneshtalab M(2013)Design space exploration for streaming applications on multiprocessors with guaranteed service NoCProceedings of the Sixth International Workshop on Network on Chip Architectures10.1145/2536522.2536527(35-40)Online publication date: 8-Dec-2013
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Stefan RNejad AGoossens K(2012)Online allocation for contention-free-routing NoCsProceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop10.1145/2107763.2107767(13-16)Online publication date: 25-Jan-2012
https://dl.acm.org/doi/10.1145/2107763.2107767
Chen ZJantsch A(2010)A worst case performance model for TDM virtual circuit in NoCsProceedings of the 2010 IFIP international conference on Network and parallel computing10.5555/1882011.1882057(452-461)Online publication date: 13-Sep-2010
https://dl.acm.org/doi/10.5555/1882011.1882057
Qian YLu ZDou WWakabayashi K(2009)Analysis of communication delay bounds for network on chipsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509639(7-12)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509639
Lu ZJantsch A(2008)TDM virtual-circuit configuration for network-on-chipIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200067316:8(1021-1034)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000673

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TDM virtual-circuit configuration for network-on-chip

Slot allocation algorithms in centralized scheduling scheme for IEEE 802.16 based wireless mesh networks

Least constraining time-slot allocation in gmpls optical tdm networks and optimization of optical buffering

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