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A self-adjusting clock tree architecture to cope with temperature variations

Published: 05 November 2007 Publication History

Abstract

Ensuring resilience against environmental variations is becoming one of the great challenges of chip design. In this paper, we propose a self adjusting clock tree architecture, SACTA, to improve chip performance and reliability in the presence of on-chip temperature variations. SACTA performs temperature dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. We present an automatic temperature adjustable skew buffer design, which enables the adaptive feature of SACTA. Furthermore, we propose an efficient and general optimization framework to determine the configuration of these special delay elements. Experimental results show that a pipeline supported by SACTA is able to prevent thermal induced timing violations within a significantly larger range of operating temperatures (enhancing the violation-free range by as much as 45°C).

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Cited By

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  • (2015)A Novel Framework for Temperature Dependence Aware Clock Skew SchedulingProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742073(367-372)Online publication date: 20-May-2015
  • (2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
  • (2010)Novel binary linear programming for high performance clock mesh synthesisProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133522(438-443)Online publication date: 7-Nov-2010
  • Show More Cited By
  1. A self-adjusting clock tree architecture to cope with temperature variations

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    cover image ACM Conferences
    ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
    November 2007
    933 pages
    ISBN:1424413826
    • General Chair:
    • Georges Gielen

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    IEEE Press

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    Published: 05 November 2007

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    ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;
    Overall Acceptance Rate 457 of 1,762 submissions, 26%

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    View all
    • (2015)A Novel Framework for Temperature Dependence Aware Clock Skew SchedulingProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742073(367-372)Online publication date: 20-May-2015
    • (2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
    • (2010)Novel binary linear programming for high performance clock mesh synthesisProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133522(438-443)Online publication date: 7-Nov-2010
    • (2010)Inversed temperature dependence aware clock skew scheduling for sequential circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871326(1657-1660)Online publication date: 8-Mar-2010
    • (2008)Automated design of self-adjusting pipelinesProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391523(211-216)Online publication date: 8-Jun-2008

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