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Exploiting hierarchy and structure to efficiently solve graph coloring as SAT

Published: 05 November 2007 Publication History

Abstract

Many important EDA problems can be formulated as graph coloring, which is a class of the Constraint Satisfaction Problem (CSP). This paper makes three contributions. First, we define new encodings for representing CSPs as equivalent Boolean Satisfiability (SAT) problems: 1) a generalization of the log encoding by using ITE trees to select the domain values of a CSP variable, so that only conflict clauses are required; and 2) a simplified direct encoding, derived from the direct encoding (where each domain value of a CSP variable is indexed by a unique Boolean variable) by omitting one of the Boolean variables and the at-least-one clause. Second, we propose the use of hierarchical encodings that combine several simple encodings to index the domain values of CSP variables, in order to produce SAT formulas that depend on fewer Boolean variables and are easier to solve. Third, we study schemes for static ordering of the Boolean variables in a Conjunctive Normal Form (CNF) representation of a CSP, based on the structure of the CSP graph, such that the resulting variable order is used for the decisions made by a SAT solver when evaluating the CNF. We compare 12 previously known SAT encodings for CSP with the two new encodings, as well as with 10 hybrid encodings. With symmetry-breaking constraints enforced, static variable ordering produced up to 2 orders of magnitude speedup. Additionally exploiting hierarchical encodings resulted in another order of magnitude speedup.

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cover image ACM Conferences
ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
November 2007
933 pages
ISBN:1424413826
  • General Chair:
  • Georges Gielen

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IEEE Press

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Published: 05 November 2007

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

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View all
  • (2019)ROADProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3309752(65-72)Online publication date: 4-Apr-2019
  • (2017)SAT Encodings of Finite-CSP DomainsProceedings of the 8th International Symposium on Information and Communication Technology10.1145/3155133.3155167(84-91)Online publication date: 7-Dec-2017
  • (2015)A New Method to Encode the At-Most-One Constraint into SATProceedings of the 6th International Symposium on Information and Communication Technology10.1145/2833258.2833293(46-53)Online publication date: 3-Dec-2015
  • (2014)Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for boolean encoding of cardinalityProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691502(676-683)Online publication date: 3-Nov-2014
  • (2014)Solving the all-interval series problemProceedings of the 5th Symposium on Information and Communication Technology10.1145/2676585.2676605(65-74)Online publication date: 4-Dec-2014
  • (2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
  • (2008)Comparison of Boolean satisfiability encodings on FPGA detailed routing problemsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403682(1268-1273)Online publication date: 10-Mar-2008

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