research-article

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs

Authors:

Roshan Weerasekera,

Dinesh Pamunuwa,

Hannu TenhunenAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 212 - 219

Published: 05 November 2007 Publication History

Abstract

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result upto 80% of the final product cost.

In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.

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Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

Publication History

Published: 05 November 2007

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ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Marinissen ERosenstiel WMacii E(2012)Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493023(1277-1282)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493023
Chen YYang CChen JHu A(2012)Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMsProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429479(458-465)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429479
Ye FChakrabarty KGroeneveld PSciuto DHassoun S(2012)TSV open defects in 3D integrated circuitsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228545(1024-1030)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228545
Salah KRagai HIsmail YRouby A(2011)Equivalent lumped element models for various n-port through silicon vias networksProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950862(176-183)Online publication date: 25-Jan-2011
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Camacho JFlich J(2011)HPC-MeshProceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems10.1109/ANCS.2011.17(69-80)Online publication date: 3-Oct-2011
https://dl.acm.org/doi/10.1109/ANCS.2011.17
Marinissen EDe Micheli GAl-Hashimi BMueller WMacii E(2010)Testing TSV-based three-dimensional stacked ICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871336(1689-1694)Online publication date: 8-Mar-2010
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Zhao JDong XXie YSapatnekar S(2010)Cost-aware three-dimensional (3D) many-core multiprocessor designProceedings of the 47th Design Automation Conference10.1145/1837274.1837308(126-131)Online publication date: 13-Jun-2010
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Jiang LHuang LXu QBenini LDe Micheli GAl-Hashimi BMueller W(2009)Test architecture design and optimization for three-dimensional SoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874672(220-225)Online publication date: 20-Apr-2009
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Seiculescu CMurali SBenini LDe Micheli GBenini LDe Micheli GAl-Hashimi BMueller W(2009)SunFloor 3DProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874626(9-14)Online publication date: 20-Apr-2009
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Murali SSeiculescu CBenini LDe Micheli GWakabayashi K(2009)Synthesis of networks on chips for 3D systems on chipsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509701(242-247)Online publication date: 19-Jan-2009
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