research-article

Strategies for improving the parametric yield and profits of 3D ICs

Authors:

R. Iris BaharAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 220 - 226

Published: 05 November 2007 Publication History

Abstract

Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ICs by reducing the communication time between different chip components through the use of short TSV-based vertical wires. This reduction is particularly attractive in processors where it is desirable to reduce the access time between the main logic die and the L2 cache or the main memory die. Process variations in 2D ICs lead to a drop in parametric yield (as measured by speed, leakage and sales profits), which forces manufacturers to speed bin their chips and to sell slow chips at reduced prices. In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and profits of 3D ICs. Comparing our proposed strategies to current yield-oblivious methods, it is demonstrated that it is possible to increase the number of 3D ICs in the fastest speed bins by almost 2x, while simultaneously reducing the number of slow ICs by 29.4%. This leads to an improvement in performance by up to 6.45% and an increase of about 12.48% in total sales revenue using up-to-date market price models.

References

[1]

{Online}. Available: www.simucad.com

[2]

{Online}. Available: http://www.eas.asu.edu/ ptm/introduction.html

[3]

{Online}. Available: http://www.spec.org/cpu/

[4]

J. Baliga, "Chips Go Vertical," IEEE Spectrum Magazine, vol. 41(3), pp. 43--47, 2004.

Digital Library

[5]

K. Banerjee, S. J. Souri, P. Kaput, and K. C. Saraswat, "3-D ICs: A Novel Chip Design for Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," Proceedings of the IEEE, vol. 89(5), pp. 602--633, 2001.

[6]

P. Benkart, A. Kaiser, A. Munding, M. Bschorr, H.-J. Pfleiderer, E. Kohn, A. Heittmann, H. Huebner, and U. Ramacher, "3D Chip Stack Technology Using Through-Chip Interconnects," IEEE Design & Test of Computers, vol. 22(6), pp. 512--518, 2005.

Digital Library

[7]

S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter Variations and Impact on Circuits and Microarchitecture," in Design Automation Conference, 2003, pp. 338--342.

Digital Library

[8]

K. Bowman, S. Duvall, and J. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE Journal of Solid State Electronics, vol. 37(2), pp. 183--190, 2002.

[9]

D. C. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.0, Tech. Rep. CS-TR-1997-1342, 1997. {Online}. Available: citeseer.ist.psu.edu/burger97simplescalar.html

Digital Library

[10]

J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," in Proc. Intl. Conference on Computer Aided Design, 2004, pp. 306--313.

Digital Library

[11]

W. Cook and A. Rohe, "Computing Minimum Weight Perfect Matchings, http://www.or.uni-bonn.de/home/rohe/matching.html," INFORMS J. Computing, vol. 11, pp. 38--148, 1999.

Digital Library

[12]

B. D. Cory, R. Kapur, and B. Underwood, "Speed Binning with Path Delay Test in 150-nm Technology," IEEE Design & Test of Computers, vol. 20(5), pp. 41--45, 2003.

Digital Library

[13]

A. Datta, S. Bhunia, J. H. Choi, S. Mukhopadhyay, and K. Roy, "Speed Binning Aware Design Methodology to Improve Profit under Parameter Variations," in Proc. Asia and South Pacific Design Automation Conference, 2006, pp. 712--717.

Digital Library

[14]

J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. Meindl, "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century," Proceedings of the IEEE, vol. 89(3), pp. 305--324, 2001.

Digital Library

[15]

W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. Sule, M. Steer, and P. D. Franzon, "Demystifying 3D ICs: The Pros and Cons of Going Vertical," IEEE Design & Test of Computers, vol. 22(6), pp. 498--510, 2005.

Digital Library

[16]

M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, first (twenty-third printing) ed. W. H. Freeman and Company, 1979.

Digital Library

[17]

B. Goplen and S. Sapatnekar, "Thermal Via Placement in 3D ICs," in Proc. Intl. Symposium on Physical Design, 2005, pp. 167--174.

Digital Library

[18]

E. Grossar, M. Stucchi, K. Maes, and W. Dehaene, "Statistically Aware SRAM Memroy Array Design," in International Symposium on Quality Electronic Design, 2006, pp. 25--30.

Digital Library

[19]

M. Healy, M. Vittes, M. Ekpanyapong, C. S. Ballapuram, K. S. Lim, H.-H. S. Lee, and G. H. Loh, "Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26(1), pp. 38--52, 2007.

Digital Library

[20]

E. Humenay, D. Arjan, and K. Skadron, "Impact of Parameter Variations on Multi-Core Chips," in Workshop on Architectural Support for Gigascale Integration, 2006, pp. 1--9.

[21]

P. Jacob, O. Erdogan, A. Zia, P. M. Belemjian, R. P. Kraft, and J. F. McDonald, "Predicting the Performance of a 3D Processor-Memory Chip Stack," IEEE Design & Test of Computers, vol. 22(6), pp. 540--547, 2005.

Digital Library

[22]

C. Kim, J.-J. Kim, I.-J. Chang, and K. Roy, "PVT-Aware Leakage Reduction for On-Die Caches with Improved Read Stability," IEEE Journal of Solid-State Circuits, vol. 41(1), pp. 170--178, 2006.

[23]

H. W. Kuhn, "The Hungarian Method for the Assignment Problem," Naval Research Logistic Quarterly, vol. 2, pp. 83--97, 1955.

[24]

S. K. Lim, "Physical Design for 3D System on Package," IEEE Design & Test of Computers, vol. 22(6), pp. 532--539, 2005.

Digital Library

[25]

C. C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari, "Bridging the Processor-Memory Performance Gap with 3D IC Technology," IEEE Design & Test of Computers, vol. 22(6), pp. 556--564, 2005.

Digital Library

[26]

D. Marculescu and E. Talpes, "Variability and Energy Awareness: A Microarchitecture-Level Perspective," in Design Automation Conference, 2005, pp. 11--16.

Digital Library

[27]

K. Meng and R. Joseph, "Process Variation Aware Cache Leakage Management," in International Symposium on Low-Power Electronics, 2006, pp. 262--267.

Digital Library

[28]

J. Munkres, "Algorithms for the Assignment and Transportation Problems," Journal of the Society of Industrial and Applied Mathematics, vol. 5(1), pp. 32--38, 1957.

[29]

M. Orshansky, L. Milnor, P. Chen, K. Keutzer, and C. Hu, "Impact of Spatial Intrachip Gate Length Variability on the Performance of High-Speed Digital Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21(5), pp. 544--553, 2002.

Digital Library

[30]

R. S. Patti, "Three-Dimensional Integrated Circuits and the Future of Systems-on-Chip Designs," Proceedings of IEEE, vol. 94(6), pp. 1214--1224, 2006.

[31]

R. R. Rao, D. Blaauw, D. Sylvester, and A. Devgan, "Modeling and Anlysis of Parametric Yield Under Power and Performance Constraints," IEEE Design & Test of Computers, vol. 22(4), pp. 376--385, 2005.

Digital Library

[32]

P. Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick, "Repeater Scaling and Its Impact on CAD," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23(4), pp. 451--463, 2004.

Digital Library

[33]

A. W. Topol, J. D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, "Three-dimensional Integrated Circuits," IBM Journal of Res. and Dev., vol. 50(4--5), pp. 491--506, 2006.

Digital Library

[34]

S. Wilton and N. P. Jouppi, "CACTI: An Enhanced Cache Access and Cycle Time Model," IEEE Journal Solid-State Circuits, vol. 31(5), pp. 677--688, 1996.

[35]

A. Zeng, J. Li, K. Rose, and R. J. Gutmann, "First-Order Performance Prediction of Cache Memory with Wafer-Level 3D Integration," IEEE Design & Test of Computers, vol. 22(6), pp. 548--555, 2005.

Digital Library

Cited By

Zhu LChaudhuri ABanerjee SMurali GVanna-Iampikul PChakrabarty KLim S(2021)Design Automation and Test Solutions for Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/347346218:1(1-49)Online publication date: 16-Nov-2021
https://dl.acm.org/doi/10.1145/3473462
Wang STahoori MChakrabarty KMarculescu DLiu F(2015)Defect Clustering-Aware Spare-TSV Allocation for 3D ICsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840863(307-314)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840863
Juan DGarg SMarculescu D(2014)Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip MultiprocessorsACM Transactions on Design Automation of Electronic Systems10.1145/263360619:4(1-23)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2633606
Show More Cited By

Strategies for improving the parametric yield and profits of 3D ICs
1. Hardware

Recommendations

Parametric yield management for 3D ICs: Models and strategies for improvement

Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ...
Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs

Near-threshold computing (NTC) circuits have been shown to offer significant energy efficiency and power benefits but with a huge performance penalty. This performance loss exacerbates if process and voltage variations are considered. In this article, ...
Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Monolithic 3D (M3D) ICs provide a way to achieve high performance and low power designs within the same technology node, thereby bypassing the need for transistor scaling. M3D ICs have multiple 2D tiers sequentially fabricated on top of each other and ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

Publisher

IEEE Press

Publication History

Published: 05 November 2007

Check for updates

Qualifiers

Research-article

Conference

ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
272
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 07 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Zhu LChaudhuri ABanerjee SMurali GVanna-Iampikul PChakrabarty KLim S(2021)Design Automation and Test Solutions for Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/347346218:1(1-49)Online publication date: 16-Nov-2021
https://dl.acm.org/doi/10.1145/3473462
Wang STahoori MChakrabarty KMarculescu DLiu F(2015)Defect Clustering-Aware Spare-TSV Allocation for 3D ICsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840863(307-314)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840863
Juan DGarg SMarculescu D(2014)Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip MultiprocessorsACM Transactions on Design Automation of Electronic Systems10.1145/263360619:4(1-23)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2633606
Jiang LXu QEklow BRosenstiel WMacii E(2012)On effective TSV repair for 3D-stacked ICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492905(793-798)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492905
Yang JPak JZhao XLim SPan D(2011)Robust clock tree synthesis with timing yield optimization for 3D-ICsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950938(621-626)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950938
Knechtel JMarkov ILienig JChang YHu J(2011)Assembling 2D blocks into 3D chipsProceedings of the 2011 international symposium on Physical design10.1145/1960397.1960417(81-88)Online publication date: 27-Mar-2011
https://dl.acm.org/doi/10.1145/1960397.1960417
Chen YNiu DXie YChakrabarty KScheffer LPhillips JHu A(2010)Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysisProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133528(471-476)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133528
Ozdemir SPan YDas AMemik GLoh GChoudhary ASapatnekar S(2010)Quantifying and coping with parametric variations in 3D-stacked microarchitecturesProceedings of the 47th Design Automation Conference10.1145/1837274.1837312(144-149)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837312
Garg SMarculescu DBenini LDe Micheli GAl-Hashimi BMueller W(2009)System-level process variability analysis and mitigation for 3D MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874772(604-609)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874772
Reda SSi ABahar RHenkel JKeshavarzi AChang NGhani T(2009)Reducing the leakage and timing variability of 2D ICs using 3D ICsProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594303(283-286)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594303
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten