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The coming of age of physical synthesis

Authors:

Charles J. Alpert,

Paul G. VillarrubiaAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 246 - 249

Published: 05 November 2007 Publication History

Abstract

Physical synthesis, the integration of logic synthesis with physical design information, was born in the mid to late 1990s, which means it is about to enter its teenage years. Today, physical synthesis tools are a major part of the EDA industry, accounting for hundreds of millions of dollars in revenue. This work looks at how technology and design trends have affected physical synthesis over the last decade and also how physical synthesis will continue to evolve on its way to adulthood.

References

[1]

C. J. Alpert, S. K. Karandikar, Z. Li, G.-J. Nam, S. T. Quay, H. Ren, C. N. Sze, P. G. Villarrubia, and M. C. Yildiz. Techniques for fast physical synthesis. Proc. of IEEE, 95(3):573--599, March 2007.

[2]

Ivan Sutherland, Robert F. Sproull, and David Harris. Logical Effort: Designing Fast CMOS Circuits. Morgan Kauffman, 1999.

Digital Library

[3]

L. Trevillyan, D. Kung, R. Puri, L. N. Reddy, and M. A. Kazda. An integrated environment for technology closure of deep-submicron IC designs. IEEE Design and Test of Computers, 21(1):14--22, Jan-Feb 2004.

Digital Library

[4]

A. E. Caldwell, A. B. Kahng, and I. L. Markov. Can recursive bisection produce routable placements. In Proc. ACM/IEEE DAC, pages 477--482, 2000.

Digital Library

[5]

H. Eisenmann and F. Johannes. Generic global placement and floorplanning. In Proc. ACM/IEEE DAC, pages 269--274, 1998.

Digital Library

[6]

G.-J. Nam, C. J. Alpert, P. Villarubbia, B. Winter, and M. Yildiz. The ISPD2005 placement contest and benchmark suite. In Proc. ISPD, pages 216--220, 2005.

Digital Library

[7]

G.-J. Nam. ISPD 2006 placement contest: Benchmark suite and results. In Proc. ISPD, page 167, 2006.

Digital Library

[8]

Natarajan Viswanathan and Chris Chu. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In Proc. ISPD, pages 26--33, 2004.

Digital Library

[9]

H. Ren, D. Z. Pan, C. J. Alpert, and P. Villarrubia. Diffusion-based placement migration. In Proc. ACM/IEEE DAC, pages 515--520, 2007.

Digital Library

[10]

Pete Osler. Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. In Proc. ISPD, pages 190--197, 2004.

Digital Library

[11]

Min Pan and Chris Chu. FastRoute 2.0: A high-quality and efficient global router. In Proc. ASPDAC, pages 250--255, 2007.

Digital Library

[12]

Chris Chu and Yiu-Chung Wong. FLUTE: Fast lookup table base rectilinear Steiner minimal tree algorithm for VLSI design. IEEE TCAD, 2007.

Digital Library

[13]

Min Pan and Chris Chu. IPR: An integrated placement and routing algorithm. In Proc. ACM/IEEE DAC, pages 59--62, 2007.

Digital Library

[14]

Jason Cong and Kwok-Shing Leung. Optimal wiresizing under the distributed Elmore delay model. In Proc. IEEE/ACM ICCAD, pages 634--639, 1993.

Digital Library

[15]

J. P. Fishburn. Shaping a VLSI wire to minimize Elmore delay. In Proc. European Design and Test Conference, 1997.

Digital Library

[16]

Charles J. Alpert, Anirudh Devgan, John Fishburn, and Stephen T. Quay. Interconnect synthesis without wire tapering. IEEE TCAD, 20(1):90--104, January 2000.

Digital Library

Cited By

Livramento VGuth CNetto RGüntzel Jdos Santos LMarculescu DLiu F(2015)Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing OptimizationProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840893(528-535)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840893
Livramento VGuth CGüntzel JJohann M(2014)A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian RelaxationACM Transactions on Design Automation of Electronic Systems10.1145/264795619:4(1-25)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2647956
Moffitt MGünther GPasnik KHenkel J(2013)Place and route for massively parallel hardware-accelerated functional verificationProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561920(466-472)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561920
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The coming of age of physical synthesis
1. Hardware

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Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

Publication History

Published: 05 November 2007

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ICCAD07

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CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Livramento VGuth CNetto RGüntzel Jdos Santos LMarculescu DLiu F(2015)Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing OptimizationProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840893(528-535)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840893
Livramento VGuth CGüntzel JJohann M(2014)A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian RelaxationACM Transactions on Design Automation of Electronic Systems10.1145/264795619:4(1-25)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2647956
Moffitt MGünther GPasnik KHenkel J(2013)Place and route for massively parallel hardware-accelerated functional verificationProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561920(466-472)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561920
Ao JDong SChen SGoto SKoh CSze C(2013)Delay-driven layer assignment in global routing under multi-tier interconnect structureProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451942(101-107)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451942
Malik JPalazzari PHemani A(2012)Effort, resources, and abstraction vs performance in high-level synthesisACM SIGARCH Computer Architecture News10.1145/2460216.246022840:5(64-69)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2460216.2460228
Moffitt MSze C(2011)Wire synthesizable global routing for timing closureProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950925(545-550)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950925
Lee TChang YWang TChang YHu J(2011)An enhanced global router with consideration of general layer directivesProceedings of the 2011 international symposium on Physical design10.1145/1960397.1960411(53-60)Online publication date: 27-Mar-2011
https://dl.acm.org/doi/10.1145/1960397.1960411
Papa DKrishnaswamy SMarkov IScheffer LPhillips JHu A(2010)SPIREProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133509(373-380)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133509
Chang YLee TWang TScheffer LPhillips JHu A(2010)GLADEProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133496(319-323)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133496
Shelar RPatyra MSaxena PChang Y(2010)Impact of local interconnects on timing and power in a high performance microprocessorProceedings of the 19th international symposium on Physical design10.1145/1735023.1735060(145-152)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.1145/1735023.1735060
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