research-article

The FAST methodology for high-speed SoC/computer simulation

Authors:

William H. Reinhart,

D. Eric Johnson,

Zheng XuAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 295 - 302

Published: 05 November 2007 Publication History

Abstract

This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs, embedded systems and standard desktop/laptop/server computer systems. The methodology partitions a simulator into (i) a functional model that simulates the functionality of the computer system and (ii) a predictive model that predicts performance and other metrics. The partitioning is crafted to map most of the parallel work onto a hardware-based predictive model, eliminating much of the complexity and difficulty of simulating parallel constructs on a sequential platform.

FAST conventions and libraries have been designed to make creating, modifying, using and measuring such simulators straightforward. We describe a prototype FAST system: a full-system, RTL-level cycle-accurate-capable computer system simulator that executes the x86 ISA, boots unmodified Linux and executes unmodified x86 applications. The prototype runs two to three orders of magnitude faster than the fastest Intel and AMD RTL-level cycle-accurate x86 software-based simulators and about six to seven times faster than RTL simulation.

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Cited By

Kim DIzraelevitz ACelio CKim HZimmer BLee YBachrach JAsanović K(2016)StroberACM SIGARCH Computer Architecture News10.1145/3007787.300115144:3(128-139)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001151
Kim DIzraelevitz ACelio CKim HZimmer BLee YBachrach JAsanović KMin SLoh G(2016)StroberProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.21(128-139)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1109/ISCA.2016.21
Krishnaiah GSilpa BPanda PKumar ADick RMadsen J(2011)Exploiting temporal decoupling to accelerate trace-driven NoC emulationProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039418(315-324)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1145/2039370.2039418
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cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

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Published: 05 November 2007

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SIGDA
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ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Kim DIzraelevitz ACelio CKim HZimmer BLee YBachrach JAsanović K(2016)StroberACM SIGARCH Computer Architecture News10.1145/3007787.300115144:3(128-139)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001151
Kim DIzraelevitz ACelio CKim HZimmer BLee YBachrach JAsanović KMin SLoh G(2016)StroberProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.21(128-139)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1109/ISCA.2016.21
Krishnaiah GSilpa BPanda PKumar ADick RMadsen J(2011)Exploiting temporal decoupling to accelerate trace-driven NoC emulationProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039418(315-324)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1145/2039370.2039418
Krishnaiah GSilpa BPanda PKumar AGivargis TDonlin A(2010)FastFwdProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1878961.1879006(247-256)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878961.1879006
Fytraki SPnevmatikatos DBenini LDe Micheli GAl-Hashimi BMueller W(2009)ReSim, a trace-driven, reconfigurable ILP processor simulatorProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874751(536-541)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874751
Vijayaraghavan MArvind A(2009)Bounded dataflow networks and latency-insensitive circuitsProceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign10.5555/1715759.1715781(171-180)Online publication date: 13-Jul-2009
https://dl.acm.org/doi/10.5555/1715759.1715781
Pellauer MAdler MChiou DEmer J(2009)Soft connectionsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629986(276-281)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629986
Pellauer MVijayaraghavan MAdler MArvind Emer J(2009)A-Port NetworksACM Transactions on Reconfigurable Technology and Systems10.1145/1575774.15757752:3(1-26)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1145/1575774.1575775
Pellauer MVijayaraghavan MAdler MArvind Emer JHutton MChow P(2008)A-PortsProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344685(87-96)Online publication date: 24-Feb-2008
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