research-article

A simultaneous bus orientation and bused pin flipping algorithm

Authors:

Fan Mo,

Robert K. BraytonAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 386 - 389

Published: 05 November 2007 Publication History

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Abstract

The orientation of a bus is defined as the direction from the Least Significant Bit (LSB) to the Most Significant Bit (MSB). Bused pin flipping is a property that allows several bused pins to flip without changing the system functionality. In this paper a simultaneous bus orientation and bused pin flipping algorithm is presented. The algorithm can be integrated into a bus-centric floorplanner targeting bus-rich designs such as microprocessors. Experimental results show that a floorplanner enhanced by the algorithm produces high quality floorplans in terms of bus routing.

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Cited By

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Liu DYu BLivramento VChowdhury SDing DVo HSharma APan D(2019)Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal GroupsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442438:6(1147-1160)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834424
Liu DLivramento VChowdhury SDing DVo HSharma APan D(2017)StreakProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062321(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062321
Wu BHo TBahar RLombardi FAtienza DBrunvand E(2010)Bus-pin-aware bus-driven floorplanningProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785489(27-32)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785489

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Macro-block pin assignment and routing are important tasks in physical design planning. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing, and 2) a net-by-net ...

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Published In

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

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IEEE Press

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Published: 05 November 2007

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ICCAD07

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CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Liu DYu BLivramento VChowdhury SDing DVo HSharma APan D(2019)Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal GroupsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442438:6(1147-1160)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834424
Liu DLivramento VChowdhury SDing DVo HSharma APan D(2017)StreakProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062321(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062321
Wu BHo TBahar RLombardi FAtienza DBrunvand E(2010)Bus-pin-aware bus-driven floorplanningProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785489(27-32)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785489

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Bus-pin-aware bus-driven floorplanning

Bus-driven floorplanning with bus pin assignment and deviation minimization

An algorithm for simultaneous pin assignment and routing

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