Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling

Automated circuit optimization is an important component of complex analog integrated circuit design. Today's analog designs must be optimized not only for nominal performance but also for robustness in order to maintain a reasonable yield with highly scaled VLSI technologies. The complex nature of analog/mixed-signal systems, however, makes this yield-aware analog circuit optimization extremely difficult and costly. In this paper, we adopt a Geostatistics motivated approach (i.e. Kriging model) for efficient extraction of yield-aware Pareto front performance models for analog circuits. An iterative search based optimization approach is proposed to efficiently seek optimal performance tradeoffs under yield constraints in high-dimensional design parameter and process variation spaces. Our experiments confirm that the generated yield-aware Pareto fronts are accurate and the optimization procedure is very efficient. The latter is achieved by the well controlled iterative update scheme in the presented techniques which avoids an excessive number of time consuming transistor-level simulations.