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Timing optimization by restructuring long combinatorial paths

Published: 05 November 2007 Publication History

Abstract

We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We show how to adapt this algorithm to logic optimization for timing correction at late stages of VLSI physical design and report experimental results on recent industrial chips. By restructuring long critical paths, our code achieves worst-slack improvements of up to several hundred picoseconds on top of traditional timing optimization techniques.

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cover image ACM Conferences
ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
November 2007
933 pages
ISBN:1424413826
  • General Chair:
  • Georges Gielen

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IEEE Press

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Published: 05 November 2007

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

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  • (2017)Fast Prefix Adders for Non-uniform Input Arrival TimesAlgorithmica10.1007/s00453-015-0067-x77:1(287-308)Online publication date: 1-Jan-2017
  • (2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
  • (2010)KL-cutsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871112(777-782)Online publication date: 8-Mar-2010
  • (2009)DeltaSynProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687546(789-796)Online publication date: 2-Nov-2009
  • (2008)Optimizing non-monotonic interconnect using functional simulation and logic restructuringProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353653(95-102)Online publication date: 13-Apr-2008

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