research-article

IntSim: A CAD tool for optimization of multilevel interconnect networks

Authors:

Deepak C. Sekar,

Jeffrey A. Davis,

James D. MeindlAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 560 - 567

Published: 05 November 2007 Publication History

Abstract

Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and die size for circuit blocks or logic cores of microchips. It includes a methodology for co-optimization of signal, power and clock interconnects, and a newly derived stochastic wiring distribution that gives reduced error than prior work when compared to measured data. Results of IntSim are found to match well with actual data from an analyzed microprocessor. Several case studies are conducted to show this CAD tool's utility as a system level simulator: (i) Wire resistivity increases due to size effects are projected to increase die size of a 22nm low power logic core by 30% and power by 7%. (ii) When compared to a 22nm low power logic core with copper interconnects, a similar logic core with carbon nanotube interconnects could reduce power by 25% and die area by 27%, or increase frequency by 15% and reduce die area by 11%. (iii) A future 22nm 8 GHz 96M gate logic core's power, die size and optimal multilevel interconnect architecture are predicted. A version of IntSim with a graphical user interface is available for download from www.ece.gatech.edu/research/labs/gsigroup.

References

[1]

N. S. Nagaraj, W. R. Hunter, P. R. Chidambaram, et al., "Impact of interconnect technology scaling on SOC design methodologies", Proc. Intl. Interconnect Technology Conference, 2005

[2]

N. Magen, A. Kolodny, U. Weiser, N. Shamir, "Interconnect power dissipation in a microprocessor", Proc. Intl. Workshop on System Level Interconnect Prediction, 2004

Digital Library

[3]

R. Puri (IBM), "3D design and CAD needs", Proc. SRC Interconnect Forum, Sep. 2006

[4]

D. Sekar, R. Venkatesan, K. Bowman, et al, "Optimal repeaters for sub-50nm interconnect networks", Proc. Intl. Interconnect Technology Conference, 2006

[5]

G. Gerosa, S. Gary, C. Dietz, et al, "A 2.2W 80MHz superscalar RISC microprocessor", J. of Solid State Circuits, Dec. 1994

[6]

W-H. Lee, A. Waite, H. Nii, et al, "High performance 65nm SOI technology with enhanced transistor strain and advanced low k BEOl,", Proc. Intl. Electron Devices Meeting, 2005

[7]

C-H. Jan, P. Bai, J. Choi, et al, "A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors", Proc. Intl. Electron Devices Meeting, 2005

[8]

R. Venkatesan, J. Davis, et al., "Optimal n tier multilevel interconnect architectures for GSI", Trans. VLSI Systems, Dec 2001

Digital Library

[9]

I. Young, K. Raol, "A comprehensive metric for evaluating interconnect performance", Proc. Intl. Interconnect Technology Conference, 2001

[10]

J. Warnock, J. Keaty, J. Petrovick, et al, "The circuit and the physical design of the POWER4 microprocessor", IBM J. of R&D, Jan. 2002

Digital Library

[11]

K. Shakeri, J. Meindl, "Compact physical IR drop models for chip package co-design of GSI", Trans. Electron Devices, Jun. 2005

[12]

Q. Chen, J. Davis, P. Zarkesh-Ha, J. Meindl, "A compact physical via blockage model", Trans. VLSI Systems, Dec. 2000

Digital Library

[13]

D. Sekar, E. Demaray, H. Zhang, P. Kohl, et al, "A new global interconnect paradigm: MIM power-ground plane capacitors", Proc. Intl. Interconnect Technology Conference, 2006

[14]

International Technology Roadmap for Semiconductors

[15]

M. Lanzerotti, G. Fiorenza, R. Rand, "Assessment of on-chip wire length distribution models", Trans. VLSI Design, Oct. 2004

Digital Library

[16]

J. Davis, V. De, J. Meindl, "Apriori wiring estimations and optimal multilevel wiring networks for portable ULSI systems", Proc. Electronic Components and Technology Conference, 1996

[17]

M. Lanzerotti, G. Fiorenza, R. Rand, "Interpretation of Rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models" Trans. VLSI Design, Dec. 2004.

Digital Library

[18]

Models in BACPAC: www.eecs.umich.edu/~dennis/bacpac

[19]

D. Stroobandt, "Apriori wire length estimates for digital design", Kluwer Academic Publishers

[20]

R. Sarvari, A. Naeemi, P. Zarkesh-Ha, J. Meindl, "Design and optimization for nanoscale power distribution networks in gigascale systems", Proc. Intl. Interconnect Technology Conference, 2007

[21]

W. Steinhogl, G. Schindler, et al, "Comprehensive Study of the Resistivity of Copper Wires With Lateral Dimensions of 100 nm and Smaller," J. of Applied Physics, 2005.

[22]

J. Davis, J. Meindl, "Interconnect technology and design for gigascale integration", Kluwer Academic Publishers

Digital Library

[23]

G. Chandra, P. Kapur, K. Saraswat, "Scaling trends for the on chip power dissipation", Proc. Intl. Interconnect Technology Conference, 2002

[24]

K. Banerjee, A. Mehrotra, "A power optimal repeater insertion methodology for global interconnects", Trans. Electron Devices, Nov. 2002.

[25]

S. Narendra, V. De, S. Borkar, D. Antoniadis, A. Chandrakasan, "Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18um CMOS," J. of Solid State Circuits, Mar. 2004.

[26]

N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, A. Kovacs, "The implementation of the 65nm dual core Merom processor", Proc. Intl. Solid State Circuits Conference, 2007

[27]

P. Bai, C. Auth, S. Balakrishnan, et al. "A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, Low k ILD and 0.57 um² SRAM cell", Proc. Intl. Electron Devices Meeting, 2004

[28]

S. Naffziger, B. Stackhouse, T. Grutkowski, "The implementation of a 2 core multi-threaded Itanium family processor", Proc. Intl. Solid State Circuits Conference, 2005

[29]

R. Sarvari, A. Naeemi, and James. D. Meindl, "Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks", Proceedings Intl. Interconnect Technology Conference, 2005

[30]

A. Naeemi, J. Meindl, "Compact physical models for multiwall carbon nanotube interconnects", Electron Device Letters, May 2006

[31]

A. Naeemi, J. Meindl, "Design and performance modeling for single walled CNTs as local, semiglobal and global interconnects in gigascale integrated systems", Trans. Electron Devices, Jan. 2007

[32]

S. Sato, M. Nihei, "Novel approach to fabricating carbon nanotube via interconnects using size-controlled catalyst nanoparticles", Proc. Intl. Interconnect Technology Conf., 2006

[33]

H. Li, W. Lu, J. Li, et al, "Multichannel ballistic transport in multiwall carbon nanotubes", Phy. Review Letters, Aug. 2005

[34]

A. Naeemi, R. Sarvari, J. Meindl, "Performance modeling and optimization for single and multiwall carbon nanotube interconnects", Proc. Design Automation Conference, 2007

Digital Library

Cited By

Huynh-Bao TRyckaert JTokei ZMercha AVerkest DThean AWambacq P(2017)Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and BeyondIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.264785325:5(1669-1680)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TVLSI.2017.2647853
Hsieh MRodrigues ARiesen RThompson KSong W(2011)A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design explorationACM SIGMETRICS Performance Evaluation Review10.1145/1964218.196422938:4(63-68)Online publication date: 29-Mar-2011
https://dl.acm.org/doi/10.1145/1964218.1964229
Kim DLim SReda SWang J(2010)Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICsProceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction10.1145/1811100.1811108(25-32)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1811100.1811108
Show More Cited By

IntSim: A CAD tool for optimization of multilevel interconnect networks
1. Hardware
2. Networks
  1. Network types
    1. Ad hoc networks

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Information

Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

Publication History

Published: 05 November 2007

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Research-article

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ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Huynh-Bao TRyckaert JTokei ZMercha AVerkest DThean AWambacq P(2017)Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and BeyondIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.264785325:5(1669-1680)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TVLSI.2017.2647853
Hsieh MRodrigues ARiesen RThompson KSong W(2011)A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design explorationACM SIGMETRICS Performance Evaluation Review10.1145/1964218.196422938:4(63-68)Online publication date: 29-Mar-2011
https://dl.acm.org/doi/10.1145/1964218.1964229
Kim DLim SReda SWang J(2010)Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICsProceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction10.1145/1811100.1811108(25-32)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1811100.1811108
Kim DMukhopadhyay SLim SCheng CReda S(2009)Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICsProceedings of the 11th international workshop on System level interconnect prediction10.1145/1572471.1572486(85-92)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1572471.1572486

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