A fast band-matching technique for interconnect inductance modeling
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Shielding effect of on-chip interconnect inductance
Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an load driven by a CMOS inverter is presented. The ...
Shielding effect of on-chip interconnect inductance
GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSIInterconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. The effective capacitance of an RLC load driven by a CMOS inverter is analytically modeled. The ...
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