research-article

Analog placement with common centroid constraints

Authors:

Qiang Ma,

Evangeline F. Y. Young,

K. P. PunAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 579 - 585

Published: 05 November 2007 Publication History

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Abstract

In order to reduce parasitic mismatch in analog circuits, some groups of devices are required to share a common centroid while being placed. Devices are split into smaller ones and placed with a common center point. We will address this problem of handling common centroid constraint in placement. A new representation called Center-based Corner Block List (C-CBL) is proposed which is a natural extension of Corner Block List (CBL) [1] to represent a common centroid placement of a set of device pairs. C-CBL is complete and non-redundant in representing any common centroid mosaic packings with pairs of blocks to be matched. To address the same problem with an additional constraint that devices are required to be placed uniformly to average out the parasitic errors, a grid-based approach is proposed. Experimental results show that both approaches are fast and promising, and have high scalability that even large data sets can be handled effectively.

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Cited By

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Wu PLin MLi XHo T(2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
https://dl.acm.org/doi/10.1145/2856031
Schlichtmann UDavoodi AYoung E(2015)Beyond GORDIAN and KraftwerkProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2723571(133-140)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2723571
Wu PLin MLi XHo TDavoodi AYoung E(2015)Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717769(25-31)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2717769
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ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

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IEEE Press

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Published: 05 November 2007

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ICCAD07

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CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Wu PLin MLi XHo T(2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
https://dl.acm.org/doi/10.1145/2856031
Schlichtmann UDavoodi AYoung E(2015)Beyond GORDIAN and KraftwerkProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2723571(133-140)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2723571
Wu PLin MLi XHo TDavoodi AYoung E(2015)Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717769(25-31)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2717769
Huang CWey CChen JLuo P(2013)Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuitsACM Transactions on Design Automation of Electronic Systems10.1145/253439419:1(1-13)Online publication date: 20-Dec-2013
https://dl.acm.org/doi/10.1145/2534394
Lin CLee CLin JChang SHu A(2012)Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuitsProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429520(635-642)Online publication date: 5-Nov-2012
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Lin CLu CLin JChang SHu JKoh C(2012)Routability-driven placement algorithm for analog integrated circuitsProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160934(71-78)Online publication date: 25-Mar-2012
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Chou POu HChang YPhillips JHu AGraeb H(2011)Heterogeneous B*-trees for analog placement with symmetry and regularity considerationsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132445(512-516)Online publication date: 7-Nov-2011
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Lin CLin JChiu YHuang CChang SStok LDutt NHassoun S(2011)Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuitsProceedings of the 48th Design Automation Conference10.1145/2024724.2024847(528-533)Online publication date: 5-Jun-2011
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Yang BDong QLi JNakatake SScheffer LPhillips JHu A(2010)Structured analog circuit design and MOS transistor decomposition for high accuracy applicationsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133582(721-728)Online publication date: 7-Nov-2010
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Xiao LYoung EHe XPun KScheffer LPhillips JHu A(2010)Practical placement and routing techniques for analog circuit designsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133572(675-679)Online publication date: 7-Nov-2010
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Analog placement with common centroid and 1-D symmetry constraints

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

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