The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip
Authors: 
Yi Wang, Dan ZhaoAuthors Info & Claims
Yi Wang, Dan ZhaoAuthors Info & ClaimsPages 612 - 617
Abstract
To bridge the widening gap between computation requirements and communication efficiency faced by gigascale heterogeneous SoCs in the upcoming ubiquitous era, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), is introduced by using the recently developed CMOS proximity wireless interconnection technology. In this paper, a synchronous and distributed medium access control (SD-MAC) protocol is designed and implemented. Tailored for WNoC, SD-MAC employs a binary countdown approach to resolve channel contention between RF nodes. The receiver_select_sender mechanism and hidden terminal elimination scheme are proposed to increase the throughput and channel utilization of the system. Our simulation study shows the promising performance of SD-MAC in terms of throughput, latency, and network utilization. As a major component of simple and compact RF node design, a MAC unit implements the proposed SDMAC that guarantees correct operation of synchronized frames while keeping overhead low. The synthesis results demonstrate several attractive features such as high speed, low power consumption, nice scalability and low area cost.
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- The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip
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- CEDA: Council on Electronic Design Automation
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE CASS/CANDE
- IEEE-CS\DATC: IEEE Computer Society
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IEEE Press
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Published: 05 November 2007
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ICCAD07
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- CEDA
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- IEEE-CS\DATC
ICCAD07: The International Conference on Computer-Aided Design 2007
November 5 - 8, 2007
California, San Jose
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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%
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