research-article

Including inductance in static timing analysis

Authors:

Ahmed Shebaita,

Dusan Petranovic,

Yehea IsmailAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 686 - 691

Published: 05 November 2007 Publication History

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Abstract

In this paper analytical expressions are derived for effective load capacitances of RLC interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS gate. The new effective capacitance calculation technique poses no extra complexity as compared to the RC based approaches but can accommodate inductance. These new expressions are derived based on a generalized driving point admittance. The generalized driving point admittance takes inductance into consideration and hence accounts for the inductive shielding that in some cases can even exceed the resistive shielding in current technologies. Another improvement in the new effective capacitance calculation method is the utilization of a more general waveform shape that accounts for the non-monotonic behavior due to inductance effects. It is shown throughout the paper that two effective capacitances are required for accurate estimation of the propagation delay and rise time with an RLC interconnect load. Simulation results show that the error in propagation delays and rise times when neglecting inductance can be over 60% as compared to an RLC model in realistic interconnects. On the other hand, simulations show that the propagation delay and rise time maximum errors associated with the proposed approach are less than 10% as compared to SPICE.

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Cited By

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Kabir MPetranovic DPeng YChen YZhirnov VSasan ASavidis I(2021)Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-DesignProceedings of the 2021 on Great Lakes Symposium on VLSI10.1145/3453688.3461505(135-140)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461505

Including inductance in static timing analysis
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ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

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IEEE Press

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Published: 05 November 2007

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ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Kabir MPetranovic DPeng YChen YZhirnov VSasan ASavidis I(2021)Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-DesignProceedings of the 2021 on Great Lakes Symposium on VLSI10.1145/3453688.3461505(135-140)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461505

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Modeling subthreshold SOI logic for static timing analysis

Inductance Analysis of On-Chip Interconnects

Crosstalk Aware Static Timing Analysis: A Two Step Approach

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