Efficient computation of current flow in signal wires for reliability analysis
Authors: 
Kanak Agarwal, Frank LiuAuthors Info & Claims
Kanak Agarwal, Frank LiuAuthors Info & ClaimsPages 741 - 746
Abstract
Electromigration (EM) and self-heating are critical reliability concerns for metal wires in high performance designs. EM reliability rules for a VLSI technology are typically expressed in terms of average, root-mean-square and peak current limits for each metal layer in the technology. To ensure EM reliability of a design, current flowing through each wire segment in the design should not violate the EM reliability rules. In this work, we present closed-from analytical models for efficient computation of average, root-mean-square and peak currents through any element in an arbitrary RC tree. The proposed models are validated against SPICE simulations for several RC nets extracted from an industrial ASIC design. The results show that the models exhibit very good accuracy with a mean error of only 3.1% in root-mean-square and 0.2% in average current estimation.
References
[1]
I. A. Belch and J. Sello, "The Failure of Thin Aluminum Current-Carrying Strips in Oxidized Silicon", Physics of Failure in Electronics, vol. 5, pp. 496--505, 1966.
[2]
J. R. Black, "Mass Transport of Aluminum by Momentum Exchange with Conduction Electrons", IEEE Intl. Reliability Physics Symp., pp. 148--159, 1967.
[3]
K. Banerjee and A. Mehrotra, "Global Interconnect Warming", IEEE Circuits and Devices Magazine, pp. 16--32, 2001.
[4]
A. R. Oriani, "Thermomigration in Solid Metals", Journal of Phys. Chem. Solids, pp. 339--351, 1969.
[5]
N. S. Nagaraj, F. Cano, H. Haznedar and D. Young, "A Practical Approach to Static Signal Electromigration Analysis", Design Automation Conf., pp. 572--577, 1998
[6]
D. Blaauw, C. Oh, V. Zolotov and A. Dasgupta, "Static Electromigration Analysis for On-Chip Signal Interconnects", IEEE Trans. on Computer-Aided Design, vol. 22, pp. 39--48, 2003.
[7]
M. Shao et al., "A Fast and Accurate Method for Interconnect Current Calculation", Asia South Pacific Design Automation Conf., pp. 37--42, 2003.
[8]
Virtuoso Analog ElectronStorm Option, Cadence Design Systems, www.cadence.com/products/custom_ic/electronstorm/index.aspx
[9]
J. E. Murguia, J. B. Brenstien, "Short-Time Failure of Metal Interconnect Caused by Current Pulses", IEEE Elec. Dev. Letters, pp. 481--483, 1993.
[10]
J. E. Hall, D. E. Hocevar, P. Yang and M. J. McGraw, "SPIDER --- A CAD System for Modeling VLSI Metallization Patterns", IEEE Trans. on Computer-Aided Design, vol. 36, pp. 1023--1031, 1978.
[11]
R. H. Tu et al., "Berkeley Reliability Tools --- BERT, IEEE Trans. on Computer-Aided Design, vol. 12, pp. 1524--1534, 1993.
[12]
D. F. Frost and K. F. Poole, "RELIANT: A Reliability Analysis Tool for VLSI Interconnects", IEEE Journal of Solid-State Circuits, vol. 24, pp. 458--462, 1989
[13]
C. Teng, Y. Cheng, E. Rosenbaum, S. Kang, "iTEM: A Temperature-Dependent Electromigration Reliability Diagnosis Tool", IEEE Trans. on Computer-Aided Design, vol. 16, pp. 882--893, 1997.
[14]
L. T. Pillage and R. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis", IEEE Trans. on Computer-Aided Design, vol. 9, pp. 352--366, 1990.
[15]
A. Odabasioglu, M. Celik and L. Pileggi, "PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm," Intl. Conf. on Computer-Aided Design, pp. 58--65, 1997.
[16]
J. J. Clement, S. P. Riege, R. Cvijetic and C. V. Thompson, "Methodology for Electromigration Critical Threshold Design Rule Evaluation", IEEE Trans. on Computer-Aided Design, vol. 18, pp. 576--581, 1999.
[17]
S. Rochel, G. Steele, J. R. Lloyd, S. Z. Hussain and D. Overhauser, "Full-Chip Reliability Analysis", IEEE Intl. Reliability Physics Symp., pp. 356--362, 1998.
[18]
C. L. Ratzlaff, N. Gopal and L. T. Pillage, "RICE: Rapid Interconnect Circuit Evaluator," Design Automation Conf., pp. 555--560, 1991.
[19]
C. J. Alpert, A. Devgan and C. Kashyap, "A two moment RC delay metric for performance optimization," Intl. Symp. on Physical Design, pp. 69--74, 2000.
[20]
T. Lin, E. Acar and L. Pileggi, "h-gamma: An RC Delay Metric Based on a Gamma Distribution Approximation to the Homogenous Response," Intl. Conf. on Computer-Aided Design, pp. 19--25, 1998.
[21]
F. Liu, C. Kashyap and C. J. Alpert, "A Delay Metric for RC circuits Based on the Weibull Distribution," Intl. Conf. on Computer-Aided Design, pp. 620--624, 2002.
[22]
C. Alpert, F. Liu, C. Kashyap and A. Devgan, "Delay and Slew Metrics Using the Lognormal Distribution", Design Automation Conf., pp. 382--385, 2003.
[23]
F. Dartu, N. Menezes and L. T. Pileggi, "Performance Computation for Precharacterized CMOS Gates with RC Loads," IEEE Trans. on Computer-Aided Design, vol. 15, pp. 544--553, 1996.
[24]
C. Amin, F. Dartu and Y. Ismail, "Weibull-Based Analytical Waveform Model", IEEE Trans. on Computer-Aided Design, vol. 24, pp. 1156--1168, 2005.
[25]
J. Qian, S. Pullela and L. T. Pillage, "Modeling the Effective Capacitance for the RC Interconnect of CMOS Gates," IEEE Trans. on Computer-Aided Design, vol. 13, pp. 1526--1535, 1994.
- Efficient computation of current flow in signal wires for reliability analysis
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Published: 05 November 2007
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ICCAD07: The International Conference on Computer-Aided Design 2007
November 5 - 8, 2007
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