skip to main content
10.5555/1326073.1326235acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
research-article

Combining static and dynamic defect-tolerance techniques for nanoscale memory systems

Published: 05 November 2007 Publication History

Abstract

Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a usable nanoscale memory system poses a significant challenge. In particular, we need to bootstrap a sea of unreliable bits into contiguous address ranges which are preferably as large as 4K-byte virtual memory pages. We accomplish this bootstrapping through a combination of dynamic error correction codes within 32-bit blocks and a static defect map which tracks usability of these blocks. The key insight is that statically-determined defect locations can be much more powerful than dynamically correcting for unknown locations, but that defect maps are only practical at a coarse granularity. Using a combination of BCH error correction codes and a Bloom-Filter-based defect map, we achieve a memory efficiency of 60% and 13% for 4K-byte pages at 1% and 10% bit-error rates, respectively.

References

[1]
Burton H. Bloom. Space/Time Trade-offs in Hash Coding with Allowable Errors. Communications of the ACM, 13(7):422--426, 1970.
[2]
A. DeHon, S. C. Goldstein, P. Kuekes, and P. Lincoln. Nonphotolithographic Nanoscale Memory Density Prospects. IEEE Transactions on Nanotechnology, 4:215--228, March 2005.
[3]
A. DeHon and K. K. Likharev. Hybrid CMOS/Nanoelectronic Digital Circuits: Devices, Architectures, and Design Automation. In ICCAD '05: Proceedings of the 2005 IEEE/ACM International Conference on Computer-Aided Design, pages 375--382, 2005.
[4]
J. Han, J. Gao, Y. Qi, P. Jonker, and J. A. B. Fortes. Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics. IEEE Design & Test, 22(4):328--339, 2005.
[5]
C. He, M. Jacome, and G. de Veciana. Scalable Defect Mapping and Configuration of Memory-Based Nanofabrics. In IEEE International High Level Design, Validation and Test Workshop (HLDVT), 2005.
[6]
ITRS. International Technology Roadmap For Semiconductors - 2006 Edition. Semiconductor Industry Association, 2006.
[7]
J. Lawrence Carter and Mark N. Wegman. Universal Classes of Hash Functions. Journal of Computer and System Sciences, 18:143--154, 1978.
[8]
C. M. Jeffery, A. Basagalar, and R. J. O. Figueiredo. Dynamic Sparing and Error Correction Techniques for Fault Tolerance in Nanoscale Memory Structures. In 4th IEEE Conference on Nanotechnology, 2004.
[9]
P. J. Kuekes, W. Robinett, G. Seroussi, and R. S. Williams. Defect-Tolerant Interconnect to Nanoelectronic Circuits: Internally Redundant Demultiplexers Based on Error-Correcting Codes. Journal of Nanotechnology, 16:869--882, June 2005.
[10]
S. Lin and D. J. Costello. Error Control Coding, Second Edition. Prentice-Hall, Inc., Upper Saddle River, NJ, USA, 2004.
[11]
M. Mishra and S. Goldstein. Defect Tolerance at the End of the Roadmap. In ITC, pages 1201--1211, 2003.
[12]
J. V. Neuman. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components. Automata Series, Editors: C. Shannon and J. McCarthy, Princeton Univ. Press, pages 43--98, 1956.
[13]
E. Ou and W. Yang. Fast Error-Correcting Circuits for Fault-Tolerant Memory. In MTDT, pages 8--12, 2004.
[14]
M. Ramakrishna, E. Fu, and E. Bahcekapili. Efficient Hardware Hashing Functions for High Performance Computers. IEEE Transactions on Computers, 48(12):1378--1381, 1997.
[15]
J. S. Reeve and K. Amarasinghe. A parallel Viterbi Decoder for Block Cyclic and Convolution Codes. Journal of Signal Processing, 86(2):273--278, 2006.
[16]
F. Sun and T. Zhang. Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Memories. In IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (Nanoarch), 2006.
[17]
M. B. Tahoori. A Mapping Algorithm for Defect-Tolerance of Recon-figurable Nano-Architectures. In ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, pages 668--672.
[18]
J. Vollrath, U. Lederer, and T. Hladschik. Compressed Bit Fail Maps for Memory Fail Pattern Classification. Journal of Electronic Testing, 17(3--4):291--297, 2001.
[19]
G. Wang, W. Gong, and R. Kastner. Defect-Tolerant Nanocomputing Using Bloom Filters. In ICCAD 2006, November 2006.
[20]
E. Witchel, J. Cates, and K. Asanović. Mondrian Memory Protection. In Proceedings of ASPLOS-X, Oct 2002.
[21]
M. Ziegler and M. Stan. CMOS/nano Co-Design for Crossbar-Based Molecular Electronic Systems. IEEE Transactions on Nanotechnology, 2:217--230, 2003.

Cited By

View all
  • (2018)A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.280996126:7(1277-1289)Online publication date: 1-Jul-2018

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
November 2007
933 pages
ISBN:1424413826
  • General Chair:
  • Georges Gielen

Sponsors

Publisher

IEEE Press

Publication History

Published: 05 November 2007

Check for updates

Qualifiers

  • Research-article

Conference

ICCAD07
Sponsor:

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 27 Jan 2025

Other Metrics

Citations

Cited By

View all
  • (2018)A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.280996126:7(1277-1289)Online publication date: 1-Jul-2018

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media