Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling

ABSTRACT

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this article, we present a hierarchical variance analysis methodology for multistage analog circuits. Starting from the process/layout level, we derive implicit hierarchical relations and extract the sensitivity information analytically. We make use of previously computed values whenever possible so as to reduce computational time. The proposed approach is particularly geared for the domain of design and test automation, where multiple runs on slightly different circuits are necessary. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

REFERENCES

• 1: Aseem Agarwal , David Blaauw , Vladimir Zolotov, Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.900, November 09-13, 2003 [doi>10.1109/ICCAD.2003.130]
• 2: Alpaydin, G., Erten, G., Balkir, S., and Dundar, G. 2000. Multi-Level optimisation approach to switched capacitor filter synthesis. IEEE Proc. Circ. Dev. Syst. 147, 4, 243--249.
• 3: Brian A. A. Antao , Arthur J. Brodersen, ARCHGEN: automated synthesis of analog systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.231-244, June 1995 [doi>10.1109/92.386223 ]
• 4: J. S. Augusto , C. F. B. Almeida, Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis, Proceedings of the 1995 European conference on Design and Test, p.605, March 06-09, 1995
• 5: Balkir, S., Dundar, G., and Ogrenci, A. S. 2003. Analog VLSI Design Automation. CRC Press.
• 6: Bilodeau, M. and Brenner, D. 1999. Theory of Multivariate Statistics. Springer.
• 7: Byungwoo Choi , D. M. H. Walker, Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.49, April 30-May 04, 2000
• 8: John R. D'Errico , Nicholas A.,Jr. Zaino, Statistical tolerancing using a modification of Taguchi's method, Technometrics, v.30 n.4, p.397-405, Nov. 1988 [doi>10.2307/1269802]
• 9: Evans, D. 1974. Statistical tolerancing: The state of the art, Part I: Background. J. Qual. Technol. 6, 4 (Oct.), 188--195.
• 10: Evans, D. 1975. Statistical tolerancing: The state of the art, Part II: Methods for estimating moments. J. Qual. Technol. 7, 1 (Jan.), 1--11.
• 11: He, Y.-G., Tan, Y.-H., and Sun, Y. 2002. A neural network approach for fault diagnosis of large-scale analogue circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems. vol. 1, 153--156.
• 12: Johns, D. and Martin, K. 1997. Analog Integrated Circuit Design. John Wiley.
• 13: Koskinen, T. and Cheung, P. 1996. Hierarchical tolerance analysis using statistical behavioral models. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 15, 5 (May), 506--516.
• 14: Xin Li , Jiayong Le , P. Gopalakrishnan , L. T. Pileggi, Asymptotic probability extraction for non-normal distributions of circuit performance, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.2-9, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382533]
• 15: Fang Liu , Jacob J. Flomenberg , Devaka V. Yasaratne , Sule Ozev, Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing, Proceedings of the conference on Design, Automation and Test in Europe, p.126-131, March 07-11, 2005 [doi>10.1109/DATE.2005.175]
• 16: Fang Liu , Sule Ozev, Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits, Proceedings of the 2005 International Conference on Computer Design, p.161-170, October 02-05, 2005 [doi>10.1109/ICCD.2005.54]
• 17: Fang Liu , Sule Ozev, Hierarchical analysis of process variation for mixed-signal systems, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120914]
• 18: Trent McConaghy , Tom Eeckelaert , Georges Gielen, CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming, Proceedings of the conference on Design, Automation and Test in Europe, p.1082-1087, March 07-11, 2005 [doi>10.1109/DATE.2005.89]
• 19: Trent McConaghy , Georges Gielen, Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
• 20: McKeon, A. and Wakeling, A. 1989. Fault diagnosis in analogue circuits using AI techniques. In Proceedings of the IEEE International Test Conference, 118--123.
• 21: Milor, L. 1998. A tutorial introduction to research on analog and mixed-signal circuit testing. IEEE Trans. Circ. Syst. II: Analog Digit. Signal Process. 45, 10 (Oct.), 1389--1407.
• 22: Milor, L. and Visvanathan, V. 1989. Detection of catastrophic faults in analog integrated circuits. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 8, 2 (Feb.), 114--130.
• 23: Salvador Mir , Bernard Courtois , Marcelo Lubaszewski , Vladimir Kolarik, Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits, Proceedings of the 1996 European conference on Design and Test, p.254, March 11-14, 1996
• 24: Michael Orshansky , Kurt Keutzer, A general probabilistic framework for worst case timing analysis, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514059]
• 25: Razavi, B. 2001. Design of Analog CMOS Integrated Circuits. McGraw-Hil.
• 26: Semiconductor Industry Association. 2005. International technology roadmap for semiconductors. http://www.itrs.net/Links/2005ITRS/Home2005.htm.
• 27: Mustapha Slamani , Bozena Kaminska, Analog Circuit Fault Diagnosis Based on Sensitivity Computation and Functional Testing, IEEE Design & Test, v.9 n.1, p.30-39, January 1992 [doi>10.1109/54.124515 ]
• 28: Taguchi, G. 1978. Performance analysis design. Int. J. Product. Res. 16, 521--530.
• 29: Tian, M. and Shi, R.-J. 2000. Worst case tolerance analysis of linear analog circuits using sensitivity bands. IEEE Trans. Circ. Syst. I: Fundam. Theory Appl. 47, 8 (Aug.), 1138--1145.
• 30: VanSlyke, R. 1963. Monte-Carlo methods and the PERT problem. Oper. Res. 11, 5 (Sept.--Oct.), 839--860.
• 31: Wang, Z., Gielen, G., and Sansen, W. 1998. Probabilistic fault detection and the selection of measurements for analog integrated circuits. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 17, 9 (Sept.), 862--872.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Reliability, Verification

Keywords:
Hierarchical variance analysis, analog circuits, parameter correlations, performance model, process variations