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A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

Published: 23 April 2008 Publication History

Abstract

The Input vector control (IVC) technique is based on the observation that the leakage current in a CMOS logic gate depends on gate input state, and a good input vector is able to minimize leakage when the circuit is in sleep mode. The gate replacement technique is a very effective method to further reduce the leakage current. In this article, we propose a fast heuristic algorithm to find a low-leakage input vector with simultaneous gate replacement. Results on MCNC91 benchmark circuits show that our algorithm produces 14% better leakage current reduction with several orders of magnitude speedup in runtime for large circuits compared to the previous state-of-the-art algorithm. In particular, the average runtime for the ten largest combinational circuits has been dramatically reduced from 1879 seconds to 0.34 seconds.

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Cited By

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  • (2016)Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI CircuitsCircuits, Systems, and Signal Processing10.1007/s00034-016-0257-z35:11(4139-4152)Online publication date: 1-Nov-2016
  • (2016)An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron CircuitsAdvanced Computing and Communication Technologies10.1007/978-981-10-1023-1_6(59-69)Online publication date: 10-Jun-2016
  • (2012)Static NBTI Reduction Using Internal Node ControlACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234884917:4(1-30)Online publication date: 1-Oct-2012
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  1. A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 2
      April 2008
      272 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/1344418
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 23 April 2008
      Accepted: 01 September 2007
      Received: 01 September 2007
      Published in TODAES Volume 13, Issue 2

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      Author Tags

      1. Input vector control
      2. gate replacement
      3. leakage reduction

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      View all
      • (2016)Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI CircuitsCircuits, Systems, and Signal Processing10.1007/s00034-016-0257-z35:11(4139-4152)Online publication date: 1-Nov-2016
      • (2016)An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron CircuitsAdvanced Computing and Communication Technologies10.1007/978-981-10-1023-1_6(59-69)Online publication date: 10-Jun-2016
      • (2012)Static NBTI Reduction Using Internal Node ControlACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234884917:4(1-30)Online publication date: 1-Oct-2012
      • (2009)Minimization of NBTI performance degradation using internal node controlProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874657(148-153)Online publication date: 20-Apr-2009
      • (2009)Power optimization with power islands synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202071728:7(1025-1037)Online publication date: 1-Jul-2009
      • (2009)Minimization of NBTI performance degradation using internal node control2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090649(148-153)Online publication date: Apr-2009

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