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ABSTRACT
We propose a new algebraic four-level expression called k-EXOR-projected sum of products (kEP-SOP). The optimization of a kEP-SOP is NPNP-hard, but can be approximated within a fixed performance guarantee in polynomial time. Moreover, fully testable circuits under the stuck-at-fault model can be derived from kEP-SOPs by adding at most a constant number of multiplexer gates. The experiments show that the computational time is very short and the results are most of the time optimal with respect to the number of products involved. kEP-SOPs also prove experimentally a good starting point for general multilevel logic synthesis.
REFERENCES
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1
|
Bernasconi, A., Ciriani, V., and Cordone, R. 2006. EXOR projected sum of products. In Proceedings of the 14th International Conference on Very Large Scale Integration.
|
 |
2
|
|
| |
3
|
Anna Bernasconi , Valentina Ciriani , Rolf Drechsler , Tiziano Villa, Efficient minimization of fully testable 2-SPP networks, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
|
| |
4
|
Bernasconi, A., Ciriani, V., Luccio, F., and Pagli, L. 2003. Three-Level logic minimization based on function regularities. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 22, 8, 1005--1016.
|
| |
5
|
|
| |
6
|
Breuer, M. and Friedman, A. 1976. Diagnosis and Reliable Design of Digital Systems. Computer Science Press.
|
| |
7
|
Caruso, G. 1991. Near optimal factorization of Boolean functions. IEEE Trans. Comput.-Aided Des. 10, 8, 1072--1078.
|
| |
8
|
Ciriani, V., Bernasconi, A., and Drechsler, R. 2006. Testability of SPP three-level logic networks in static fault models. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 25, 10, 2241--2248.
|
| |
9
|
Cordone, R., Ferrandi, F., Sciuto, D., and Wolfler Calvo, R. 2001. An efficient heuristic approach to solve the unate covering problem. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 20, 12 (Dec.), 1377--1388.
|
| |
10
|
|
| |
11
|
|
| |
12
|
Debnath, D. and Vranesic, Z. 2003. A fast algorithm for OR-AND-OR synthesis. IEEE Trans. Comput.-Aided Des. 22, 9, 1166--1176.
|
| |
13
|
Drechsler, R., Shi, J., and Fey, G. 2004. Synthesis of fully testable circuits from BDDs. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 23, 3, 440--443.
|
| |
14
|
Dubrova, E. and Ellervee, P. 1999. A fast algorithm for three-level logic optimization. In Proceedings of the International Workshop on Logic Synthesis, 251--254.
|
| |
15
|
Dubrova, E., Miller, D., and Muzio, J. 1999. AOXMIN-MV: A heuristic algorithm for AND-OR-XOR minimization. In Proceedings of the 4th International Workshop on the Applications of the Reed Muller Expansion in Circuit Design, 37--54.
|
| |
16
|
|
| |
17
|
|
| |
18
|
Ishikawa, R., Hirayama, T., Koda, G., and Shimizu, K. 2004. New three-level boolean expression based on EXOR gates. IEICE Trans. Inf. Syst. 5, 1214--1222.
|
| |
19
|
Ishikawa, R., Igarashi, T., Hirayama, T., and Shimizu, K. 2002. Pseudocube-Based expressions to enhance testability. In Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, vol. 2, 305--310.
|
| |
20
|
|
| |
21
|
|
| |
22
|
McGeer, P., Sanghavi, J., Brayton, R., and Sangiovanni-Vincentelli, A. 1993. Espresso-Signature: A new exact minimizer for logic functions. IEEE Trans. VLSI 1, 4, 432--440.
|
| |
23
|
Rudell, R. and Sangiovanni-Vincentelli, A. 1987. Multiple-valued minimization for PLA optimization. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 6, 727--750.
|
| |
24
|
Sasao, T. 1995. A design method for AND-OR-EXOR three level networks. In Proceedings of the International Workshop on Logic Synthesis. 8, 11--8:20.
|
| |
25
|
|
| |
26
|
Sentovich, E., Singh, K., Lavagno, L., Moon, C., R. Murgai, A. S., Savoj, H., Stephan, P., Brayton, R., and Sangiovanni-Vincentelli, A. 1992. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB-ERL M92-41. University of California at California.
|
| |
27
|
|
| |
28
|
Umans, C., Villa, T., and Sangiovanni-Vincentelli, A. 2006. Complexity of two-level logic minimization. IEEE Trans. Comput.-Aided Des. 25, 7, 1230--1246.
|
| |
29
|
Yang, S. 1991. Logic synthesis and optimization benchmarks user guide, version 3.0. Microelectronic Center.
|
|