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Modeling routing demand for early-stage FPGA architecture development
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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays table of contents
Monterey, California, USA
SESSION: Architecture tools table of contents
Pages 139-148  
Year of Publication: 2008
ISBN:978-1-59593-934-0
Authors
Wei Mark Fang  University of Toronto, Toronto, ON, Canada
Jonathan Rose  University of Toronto, Toronto, ON, Canada
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to do in the early stages of architecture development, however, because there is no complete architecture to synthesize circuits into. The effort required to create prototype tools for nascent architectures is far too great for every new logic block or routing architecture idea, and so it would be extremely helpful to have a simple and intuitive FPGA interconnect model to guide the architect

In this paper we present such an interconnect model for island-style FPGAs, whose single output is the estimated routing demand (often referred to as W, the number of routing tracks per channel) for an FPGA as a function of several logic block, circuit and routing architecture parameters. The goal of this model is to be as simple as possible, while still accurate enough to be useful, to provide understanding and intuition on FPGA routing. Our methodology is empirical -- we propose model forms based on empirical observations, intuition and some derivation, and then fit models to experimentally generated data

We show the development of the model in stages, beginning with a fully flexible FPGA, and gradually proceeding to one which includes the key parameters that control the flexibility of FPGA routing, and one key parameter describing the logic block and another relating to the typical circuit. We then show how to use these models in early-stage architecture development to provide feedback on several aspects of logic block architecture. We also show how the model can be used to explore the routing architecture space itself and to provide an overall intuition for architecture development


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Wei Mark Fang: colleagues
Jonathan Rose: colleagues