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Experiences using adaptive concurrency in transactional memory with Lee's routing algorithm

Published: 20 February 2008 Publication History

Abstract

Experience in profiling Lee's routing algorithm, a new complex TM application, showed that transactional applications may exhibit dynamic exploitable parallelism, i.e. the amount of useful parallelism available at any point in time varies during the execution of the application. Obviously, executing too many transactions at times when the available parallelism is low will lead to high contention and wasted computation in aborted transactions, and vice versa. Current Transactional Memory (TM) implementations do not account for this behavior.
This work employs adaptive concurrency to dynamically adjust the number of threads executing transactions concurrently. Our preliminary evaluation is performed in DSTM2 using Lee's routing algorithm, both of which were simple to modify to enable adaptive concurrency, and shows significant reduction in resource usage, and modest performance gains.

References

[1]
William Scherer III and Michael Scott, Contention Management in Dynamic Software Transactional Memory, Proceedings of the ACM PODC Workshop on Concurrency and Synchronization in Java Programs, St. John's, NL, Canada, Jul, 2004.
[2]
Maurice Herlihy and Victor Luchangco and Mark Moir, A flexible framework for implementing software transactional memory, OOPSLA '06
[3]
: Proceedings of the 21st Annual Conference on Object-Oriented Programming Systems, Languages, and Applications, Portland, Oregon, USA, Oct, 2006.
[4]
Ian Watson and Chris Kirkham and Mikel Lujan, A Study of a Transactional Parallel Routing Algorithm, PACT '07: Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques, Brasov, Romania, Sept, 2007.
[5]
Mohammad Ansari and Christos Kotselidis and Kimberly Jarvis and Mikel Lujan and Chris Kirkham and Ian Watson, Adaptive Concurrency Control for Transactional Memory, Technical Report CSPP-43, School of Computer Science, University of Manchester, Sept, 2007.

Cited By

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  • (2013)ARV–ALA: Improving performance of software transactional memory through adaptive read and write policiesScience of Computer Programming10.1016/j.scico.2012.11.00778:9(1559-1571)Online publication date: Sep-2013
  • (2010)Transactional Memory, 2nd editionSynthesis Lectures on Computer Architecture10.2200/S00272ED1V01Y201006CAC0115:1(1-263)Online publication date: 22-Dec-2010
  • (2010)Handling Conflicts with Compiler's Help in Software Transactional Memory SystemsProceedings of the 2010 39th International Conference on Parallel Processing10.1109/ICPP.2010.56(482-491)Online publication date: 13-Sep-2010
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cover image ACM Conferences
PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
February 2008
308 pages
ISBN:9781595937957
DOI:10.1145/1345206
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 20 February 2008

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Author Tags

  1. DSTM2
  2. adaptive concurrency
  3. transactional memory

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Cited By

View all
  • (2013)ARV–ALA: Improving performance of software transactional memory through adaptive read and write policiesScience of Computer Programming10.1016/j.scico.2012.11.00778:9(1559-1571)Online publication date: Sep-2013
  • (2010)Transactional Memory, 2nd editionSynthesis Lectures on Computer Architecture10.2200/S00272ED1V01Y201006CAC0115:1(1-263)Online publication date: 22-Dec-2010
  • (2010)Handling Conflicts with Compiler's Help in Software Transactional Memory SystemsProceedings of the 2010 39th International Conference on Parallel Processing10.1109/ICPP.2010.56(482-491)Online publication date: 13-Sep-2010
  • (2009)Taking the heat off transactionsProceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing10.1109/IPDPS.2009.5161032(1-10)Online publication date: 23-May-2009

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