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RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm

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Published:13 April 2008Publication History

ABSTRACT

Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical to success. We present a new physical synthesis optimization for latch placement called RUMBLE (Rip Up and Move Boxes with Linear Evaluation) that uses a linear timing model to optimize timing by simultaneously re-placing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. Experimental results validate the effectiveness of the approach: our techniques improve slack by 41.3% of cycle time on average for a large commercial ASIC design

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              cover image ACM Conferences
              ISPD '08: Proceedings of the 2008 international symposium on Physical design
              April 2008
              218 pages
              ISBN:9781605580487
              DOI:10.1145/1353629

              Copyright © 2008 ACM

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 13 April 2008

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