A robust approach to lithography friendly design implementation

ABSTRACT

A Lithography Friendly Design solution entails the creation of a single physical layout which satisfies design constraints while concurrently accounting for process and manufacturing variations. At 45nm and below, above and beyond exponential growth in complexity (and mask-size), Optical Proximity Correction fails to render certain layout topologies. Thus a degree of Lithography Friendly Design (via a lithography metric) and awareness has to be built into physical-design. The current pattern of geometric growth in classic Design Rule Checks (to help OPC), their interdependence, and ranged-interpretation strongly indicates the need for a top-down fabrication-aware physical-design methodology. Even the simple assumption about local-placement context-independence of cells is no longer valid. The mere adjacency of certain standard cells leads to degradation in yield and performance. Thus, even the domain of standard-cell placement and optimization, physical-synthesis, is affected by these lithographic phenomena

This talk focuses on the challenges faced, and approaches taken, in designing a system to address degradations in yield and performance due to these physical effects. A pragmatic approach that unifies global design optimization with yield/lithography metrics requires careful attention through-out the design flow. Understanding the interdependence between lithographic-correction and physical-design timing-closure is essential for robust solutions. Their interdependence translates into recognizing the need for accurate analysis and the generation of robust models. We show how this analysis and modeling folds the optimization of lithographic effects, and their impact, into several global algorithms that concurrently optimize for Timing, Power and Signal Integrity. As implemented, they drastically reduce the number of lithographic violations at signoff, leaving the few remaining to be fixed with a highly adaptable cross-probe, annotate and repair mechanism

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation; Placement and routing

General Terms:
Algorithms, Design