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A robust, fast pulsed flip-flop design

Published: 04 May 2008 Publication History

Abstract

High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip-flops. In this paper, we present a pulsed flip-flop design based on a novel pulse generator circuit. Our design achieves significantly improved speed when compared to recent pulsed flip-flop design, as well as a traditional master-slave D flip-flop. Monte Carlo simulations demonstrate that our design is significantly more robust to variations than the other flip-flops. Our design consumes low power as well. Also we have performed the layout of our design and shown that our layout area is smaller than a traditional D flip-flop.

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    cover image ACM Conferences
    GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI
    May 2008
    480 pages
    ISBN:9781595939999
    DOI:10.1145/1366110
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 04 May 2008

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    Author Tags

    1. flip-flop
    2. latch

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    May 4 - 6, 2008
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    • (2021)Resonance-Based Power-Efficient Pulse Generator Design with Corresponding Distribution Network2021 IEEE 39th International Conference on Computer Design (ICCD)10.1109/ICCD53106.2021.00063(357-360)Online publication date: Oct-2021
    • (2014)Pulsed-Latch Utilization for Clock-Tree Power OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225221122:4(721-733)Online publication date: 1-Apr-2014
    • (2013)Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock GatingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.223482832:2(242-246)Online publication date: 1-Feb-2013
    • (2012)Novel pulsed-latch replacement based on time borrowing and spiral clusteringProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160944(121-128)Online publication date: 25-Mar-2012
    • (2011)Pulsed-latch-based clock tree migration for dynamic power reductionProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016813(39-44)Online publication date: 1-Aug-2011
    • (2011)Statistical Design Framework of Submicron Flip-Flop Circuits Considering Process VariationsIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2010.208069324:1(69-79)Online publication date: Feb-2011
    • (2011)Retiming Pulsed-Latch Circuits With Regulating Pulse WidthIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.212693230:8(1114-1127)Online publication date: 1-Aug-2011
    • (2011)Pulsed-latch-based clock tree migration for dynamic power reductionIEEE/ACM International Symposium on Low Power Electronics and Design10.1109/ISLPED.2011.5993601(39-44)Online publication date: Aug-2011
    • (2011)A fully on-chip throughput measurement system for multi-gigabits/s on-chip interconnects2011 3rd Asia Symposium on Quality Electronic Design (ASQED)10.1109/ASQED.2011.6111713(119-124)Online publication date: Jul-2011

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