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Pipelined network of PLA based circuit design

Published: 04 May 2008 Publication History

Abstract

In this paper, we present a pipelined Network of PLA based circuit design approach. Our approach can be used to realize an arbitrary logic circuit with an extremely high throughput and low latency. Using logic synthesis tools to decompose a logic circuit into this framework, and appropriately inserting "stutter" blocks to balance the logical depth of all paths in the decomposed circuit, we come up with a pipelined network of PLA netlist. We have demonstrated the effectiveness of the approach via SPICE simulations and layout generation experiments. Throughput, latency, and area are compared with competing approaches, demonstrating the power of this design style. We show that our approach has a 75% better throughput than the asynchronous micropipelining based technique, and a latency which is 63% that of the asynchronous scheme. Both techniques were implemented in a super-threshold fashion. We have also conducted Monte Carlo experiments to validate the approach under variations.

References

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S. Khatri, R. Brayton, and A. Sangiovanni-Vincentelli, "Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric," in Proceedings, IEEE/ACM International Conference on Computer Aided Design, pp. 412--418, Nov 2000.
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  1. Pipelined network of PLA based circuit design

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    cover image ACM Conferences
    GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI
    May 2008
    480 pages
    ISBN:9781595939999
    DOI:10.1145/1366110
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 04 May 2008

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    Author Tags

    1. PLA
    2. pipelining
    3. synchronous

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    May 4 - 6, 2008
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