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A lithography-friendly structured ASIC design approach

Published: 04 May 2008 Publication History

Abstract

Integrated circuit manufacturing costs are increasing with decreasing device feature sizes, due to significant increases in mask costs. At the same time, systematic processing variations due to optical proximity effects are also increasing, making it harder to predict the circuit behavior with fidelity. Therefore, there is a need to implement designs using regular circuit structures. In this paper, we present a new structured ASIC approach which utilizes an array of 2-input NAND gates. Our NAND2 array based circuit implementation reduces manufacturing costs, and design turn-around times because different designs can share the same masks up to the poly layer. The regular layout structure of our NAND2 array also helps in reducing systematic variations. We compared the performance of our NAND2 array with the ASIC approach by implementing several benchmark circuits using both methods. The experimental results demonstrate that on average, our approach has a delay penalty of 40%, an area penalty of 12%, and a power increase of 7%, compared to an ASIC design approach. This is better than the previously reported structured ASIC approaches. We also performed lithographical simulations of the poly and metal masks of the designs implemented using our approach as well as the ASIC design approach. These lithographical simulation results demonstrate that our approach has lower errors on the poly and the Metal1 layers by 7% and 24% respectively, compared to the ASIC approach.

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  • (2014)HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask PatterningIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2013.226469061:1(146-159)Online publication date: Jan-2014
  • (2014)A regular fabric design methodology for applications requiring specific layout-level design rulesMicroelectronics Journal10.1016/j.mejo.2013.11.00245:2(217-225)Online publication date: Feb-2014
  • (2013)Architecture and design flow for a highly efficient structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219047821:3(424-433)Online publication date: 1-Mar-2013
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    cover image ACM Conferences
    GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI
    May 2008
    480 pages
    ISBN:9781595939999
    DOI:10.1145/1366110
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 04 May 2008

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    Author Tags

    1. ASIC
    2. OPC
    3. lithography

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    View all
    • (2014)HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask PatterningIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2013.226469061:1(146-159)Online publication date: Jan-2014
    • (2014)A regular fabric design methodology for applications requiring specific layout-level design rulesMicroelectronics Journal10.1016/j.mejo.2013.11.00245:2(217-225)Online publication date: Feb-2014
    • (2013)Architecture and design flow for a highly efficient structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219047821:3(424-433)Online publication date: 1-Mar-2013
    • (2012)Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217071220:12(2184-2197)Online publication date: 1-Dec-2012
    • (2012)A reference low-complexity structured ASIC2012 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2012.6271867(2709-2712)Online publication date: May-2012
    • (2010)Power gating design for standard-cell-like structured ASICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871048(514-519)Online publication date: 8-Mar-2010
    • (2010)Via configurable three-input lookup-tables for structured ASICsProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785494(49-54)Online publication date: 16-May-2010
    • (2010)Clock routing for structured ASICs with via-configurable fabrics2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450489(777-784)Online publication date: Mar-2010
    • (2010)Structured ASIC: Methodology and comparison2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681422(377-380)Online publication date: Dec-2010
    • (2010)Power gating design for standard-cell-like structured ASICs2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)10.1109/DATE.2010.5457152(514-519)Online publication date: Mar-2010
    • Show More Cited By

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