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View all- Nahtigal TPuhar PEmva A(2012)A systematic approach to configurable functional verification of HW IP blocks at transaction levelComputers and Electrical Engineering10.1016/j.compeleceng.2012.05.00638:6(1513-1523)Online publication date: 1-Nov-2012
- Bombieri NFummi FGuarnieri V(2010)Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip10.1109/VLSISOC.2010.5642620(61-66)Online publication date: Sep-2010
- Bombieri NFummi FGuarnieri V(2010)Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)10.1109/HLDVT.2010.5496652(105-112)Online publication date: Jun-2010