ABSTRACT
In high performance designs, speed-limiting logic paths (speedpaths) impact the power/performance trade-off that is becoming critical in our low power regimes. Timing tools attempt to model and predict the delay of all the paths on a chip, which may be in the millions. These delay predictions often have a significant error and when silicon is measured there is a large variation of path delays as compared to the prediction of the tools. This variation may be caused by process, environmental or other effects that are often unpredictable. It is therefore desirable to use early silicon data to better predict and model potential speedpaths for subsequent silicon steppings. In this paper, we present a novel machine learning-based approach that uses a small number of identified speedpaths to predict a larger set of potential speedpaths, thus significantly enhancing the traditional timing prediction flows post-silicon. We demonstrate the feasibility of this approach and summarize our findings based on the analysis of silicon speedpaths from a 65nm P4 microprocessor.
- L. Lee, L. Wang, P. Parvathala, TM Mak, "On Silicon-Based Speed Path Identification," Proc. VTS 2005. Google ScholarDigital Library
- P. Bastani, B. Lee, L. Wang, M. Abadir, "Analyzing the risk of timing modeling based on path delay test," Proc. ITC, 2007.Google Scholar
- Li-C. Wang, P. Bastani, M. Abadir, "Design-silicon timing correlation -- a data mining perspective," Proc. DAC, 2007. Google ScholarDigital Library
- K. Killpack, C. Kashyap, E. Chiprout, "Silicon Speedpath Measurement and Feedback into EDA flows," Proc. DAC, 2007. Google ScholarDigital Library
- B. Gottlieb, et al, "Silicon Debug: What Do You Do When Your ASIC Does Not Work as Fast as Expected?" Proc. DAC, 2004.Google Scholar
- A. Agarwal, D. Blaauw, and F. Dartu, "Statistical Gate Delay Model Considering Multiple Input Switching," Proc. DAC, 2004. Google ScholarDigital Library
- D. Barton, P. Tangyunyong, J. Soden, A. Liang, F. Low, et al, "Infrared Light Emission From Semiconductor Devices," ISTFA Proc. 1996.Google Scholar
- P. Larsson and C. Svensson, "Noise in digital dynamic CMOS circuits," IEEE J. Solid-State Circuits June 1994, pp. 655--663.Google ScholarCross Ref
- Sanjay Pant, Eli Chiprout, "Power Grid Physics and Implications for CAD," Proc. DAC 2006. Google ScholarDigital Library
- N. Cristianini, and J. Shawe-Taylor, "An Introduction to Support Vector Machine," Cambridge University Press, 2002. Google ScholarDigital Library
- Vladamir Vapnik, "The nature of Statistical Learning Theory," 2nd editions, Springer, 1999. Google ScholarDigital Library
Index Terms
- Speedpath prediction based on learning from a small set of examples
Recommendations
Speedpath analysis based on hypothesis pruning and ranking
DAC '09: Proceedings of the 46th Annual Design Automation ConferenceIn optimizing high-performance designs, speed limiting paths (speed-paths) impact the performance and power trade-off. Timing tools attempt to model and capture all such paths on a chip. Due to the high performance nature of these designs, critical ...
Silicon feedback to improve frequency of high-performance microprocessors: an overview
ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided DesignIn modern high-performance microprocessors designed using advanced process technologies, the frequency of the part is often slower than what the static timing analysis tools predict before tape out. We give an overview of techniques used to observe the ...
Silicon speedpath measurement and feedback into EDA flows
DAC '07: Proceedings of the 44th annual Design Automation ConferenceTiming, test, reliability, and noise are modeled and abstracted in our design and verification flows. Specific EDA algorithms are then designed to work with these abstracted models, often in isolation of other effects. However, tighter design margins ...
Comments