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Layout-aware scan chain reorder for launch-off-shift transition test coverage

Published: 03 October 2008 Publication History

Abstract

Launch-off-shift (LOS) is a popular delay test technique for scan-based designs. However, it is usually not possible to achieve good delay fault coverage in LOS test due to conflicts in test vectors. In this article, we propose a layout-based scan chain ordering method to improve fault coverage for LOS test with limited routing overhead. A fast and effective algorithm is used to eliminate conflicts in test vectors while at the same time restrict the extra scan chain routing. This approach provides many advantages. (1) The proposed method can improve delay fault coverage for LOS test. (2) With layout information taken into account, the routing penalty is limited, and thus the impact on circuit performance will not be significant. Experimental results show that the proposed LOS test method achieves about the same level of delay fault coverage as enhanced scan does, while the average scan chain wire length is about 2.2 times of the shortest scan chain.

References

[1]
Boese, K. D., Kahng, A. B., and Tsay, R.-S. 1994. Scan chain optimization: Heuristic and optimal solutions, UCLA CS Dept. Internal Report.
[2]
Bonhomme, Y., Girard, Landrault, C., and Pravossoudovitch, S. 2002. Power driven chaining of flip-flops in scan architectures. In Proceedings of the International Test Conference, pp. 796--803.
[3]
Bonhomme, Y., Girard, P., Guiller, L., Landrault, C., and Pravossoudovitch, S. 2003. Efficient scan chain design for power minimization during scan testing under routing constraint. In Proceedings of the International Test Conference, pp. 488--493.
[4]
Cheng, K. T., Devadas, S., and Keutzer, K. 1991. A partial enhanced-scan approach to robust delay-fault test generation for sequential circuits. In Proceedings of the International Test Conference, pp. 403--410.
[5]
Gupta, P., Kahng, A. B., and Mantik, S. 2003. Routing-aware scan chain ordering. In Proceedings of the Asia Pacific Design Automation Conference, pp. 857--862.
[6]
Gupta, P., Kahng, A. B., Mandoiu, I. I., and Sharma, P. 2005. Layout-aware scan chain synthesis for improved path delay fault coverage. IEEE Trans. Comput.-Aided Des. 24(7), 1104--1114.
[7]
Hsiao, M. S. 2006. Test Generation. In VLSI Test Principles and Architectures: Design for Testability, L.-T. Wang, C.-W. Wu, and X. Wen, Eds. Morgan-Kaufmann, 161--262.
[8]
Kajihara, S., Morishima, S., Takuma, A., Wen, X., Maeda, T., Hamada, S., and Sato, Y. 2006. A framework of high-quality transition fault ATPG for scan circuits. In Proceedings of the International Test Conference, Paper 2.1.
[9]
Kristic, A. and Cheng, K. T. 1998. Delay Fault Testing for VLSI Circuits. Kluwer, Norwell, MA.
[10]
Leenstra, J., Koch, M., and Schwederski, T. 1993. On scan path design for stuck-open and delay fault detection. In Proceedings of the European Test Conference, pp. 201--210.
[11]
Li, W., Wang, S., Chakradhar, S. T., and Reddy, S. M. 2005. Distance restricted scan chain reordering to enhance delay fault coverage. In Proceedings of the International Conference on VLSI Design, pp. 471--478.
[12]
Liu, X., Hsiao, M. S., Chakravarty, S., and Thadikaran, P. J. 2005. Efficient techniques for transition testing. ACM Trans. Design Automa. Electronic Systems 10, 112, 258--278.
[13]
Mao, W. and Ciletti, M. D. 1990. Arrangement of latches in scan-path design to improve delay fault coverage. In Proceedings of the International Test Conference, pp. 387--393.
[14]
Polian, I. and Becker, B. 2003. Multiple scan chain design for two-pattern testing. J. Electronic Testing 19(1), 37--48, 2003.
[15]
Pomeranz, I. and Reddy, S. M. 2002. On the coverage of delay faults in scan designs with multiple scan chains. In Proceedings of the International Conference on Computer Design, pp. 206--209.
[16]
Savir, J. 1992. Skewed-load transition test: Part I, calculus. In Proceedings of the International Test Conference, pp. 705--713.
[17]
Savir, J. and Patil, S. 1994. Broad-Side delay test. IEEE Trans. Comput.-Aided Des., 13, 118, 1057--1064.
[18]
Waicukauski, J. A., Lindbloom, E., Rosen, B. K., and Iyengar, V. S. 1987. Transition fault simulation. IEEE Design and Test 4, 32--38.

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            cover image ACM Transactions on Design Automation of Electronic Systems
            ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 4
            September 2008
            328 pages
            ISSN:1084-4309
            EISSN:1557-7309
            DOI:10.1145/1391962
            Issue’s Table of Contents
            Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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            Publication History

            Published: 03 October 2008
            Accepted: 01 March 2008
            Revised: 01 January 2008
            Received: 01 August 2007
            Published in TODAES Volume 13, Issue 4

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            Author Tags

            1. Scan test
            2. scan chain ordering
            3. test generation
            4. transition faults

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