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Effective decap insertion in area-array SoC floorplan design

Published: 03 October 2008 Publication History

Abstract

As VLSI technology enters the nanometer era, supply voltages continue to drop due to the reduction of power dissipation, but it makes power integrity problems even worse. Employing decoupling capacitances (decaps) in floorplan stage is a common approach to alleviating supply noise problems. Previous researches overestimate the decap budget and do not fully utilize the empty space of the floorplan. A floorplan usually has a lot of available space that can be used to insert the decap without increasing the floorplan area. Therefore, the goal of this work is to develop a better model to calculate the required decap to solve the power supply noise problem in area-array based designs, and increase the usage of available space in the floorplan to reduce the area overhead caused by decap insertion. The experimental results of this work are encouraging. Compared with previous approaches, our methodology reduces 38% of the decap budget in average for MCNC benchmarks but can still meet the power supply noise requirements. The final floorplan areas with decap are also smaller than the numbers reported in previous works.

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Cited By

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  • (2013)A decap placement methodology for reducing joule heating and temperature in PSN interconnect2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2013.6674780(840-843)Online publication date: Aug-2013
  • (2011)Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigationACM Transactions on Design Automation of Electronic Systems10.1145/2003695.200370616:4(1-25)Online publication date: 27-Oct-2011

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cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 4
September 2008
328 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/1391962
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 October 2008
Accepted: 01 May 2008
Revised: 01 September 2007
Received: 01 May 2007
Published in TODAES Volume 13, Issue 4

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Author Tags

  1. Power supply noise
  2. decap insertion
  3. floorplan

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  • (2013)A decap placement methodology for reducing joule heating and temperature in PSN interconnect2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2013.6674780(840-843)Online publication date: Aug-2013
  • (2011)Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigationACM Transactions on Design Automation of Electronic Systems10.1145/2003695.200370616:4(1-25)Online publication date: 27-Oct-2011

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