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Enhancing beneficial jitter using phase-shifted clock distribution

Published: 11 August 2008 Publication History

Abstract

Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.

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Cited By

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  • (2010)Analysis of power supply induced jitter in actively de-skewed multi-core systems2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450490(785-790)Online publication date: Mar-2010

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      cover image ACM Conferences
      ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design
      August 2008
      396 pages
      ISBN:9781605581095
      DOI:10.1145/1393921
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      Published: 11 August 2008

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      1. clock jitter
      2. resonant supply noise

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      • (2010)Analysis of power supply induced jitter in actively de-skewed multi-core systems2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450490(785-790)Online publication date: Mar-2010

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