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SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes

Published: 11 August 2008 Publication History

Abstract

We present a novel power-aware yield enhancement design methodology and reconfiguration scheme for deep submicron SRAM designs. We show that with the continued trend of raising array supply to counter process variations, it is more effective to use a per-element selectable virtual power-supply scenario as opposed to single array supply with traditional redundancy schemes. The element can be a bank, a sub-array, or an independent row/column, and the element's virtual supply value is determined based on fail bitmaps. The technique can also be used in conjunction with traditional redundancy schemes to further improve the efficiency. The supply and redundancy assignments can be obtained by relying on memory reconfiguration algorithms. For this, we propose a greedy yet accurate algorithm that runs in O(nlogn) as opposed to average case O(n2) traditional algorithms. The methodology leads to significant power savings ranging from 20% to 50% for 65nm technology. We expect the savings to increase in future technologies as leakage powers dominate. To the best of our knowledge, this is the first time such a methodology is applied to SRAM designs.

References

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R. V. Joshi et al., "A low power and high-performance SOI SRAM circuit design with improved cell stability", SOI Conf. 2006, pp. 211 -- 214.
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A. J. Bhavnagarwala, T. Xinghai, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", IEEE JSSC, vol. 36, no. 4, pp. 658--665, April 2001.
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J. Chang et al., "The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series" JSSCC, April 2007.
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J. Davis et al., "A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor", IEEE ISSCC 2006.
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W. Shi and W. K. Fuchs, "Probabilistic Analysis and Algorithms for Reconfiguration of Memory arrays", IEEE Trans. On CAD, vol 11. no. 9, Sept. 1992.
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R. Kanj et al., Design Automation Conference, July 2006 pp. 69--72.

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  1. SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes

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    cover image ACM Conferences
    ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design
    August 2008
    396 pages
    ISBN:9781605581095
    DOI:10.1145/1393921
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 11 August 2008

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    Author Tags

    1. SRAM
    2. cover algorithm
    3. memory reconfiguration
    4. power
    5. redundancy
    6. vritual supply
    7. yield

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