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A probabilistic technique for full-chip leakage estimation

Authors:

Qing WuAuthors Info & Claims

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

Pages 205 - 208

https://doi.org/10.1145/1393921.1393975

Published: 11 August 2008 Publication History

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Abstract

In this paper, we propose a probability-based algorithm to estimate full-chip leakage without knowing layout information, under intra-die and inter-die process variations. Through modeling process variations into a random vector, we show that the standard cell leakage can be modeled as an inverse Gaussian random variable and further demonstrate that full-chip leakage can also be approximated to be an inverse Gaussian random variable. Hence, the leakage estimation problem is reduced to the estimation of the mean value and variance of the full-chip leakage. Experimental results show that the proposed algorithm is over 1000X faster than Monte Carlo simulation while the maximum estimation error is less than 6%.

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Kheirallah RGalliere JAzemard NDucharme G(2018)Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2018.8464159(88-91)Online publication date: Jul-2018
https://doi.org/10.1109/PATMOS.2018.8464159
Kheirallah RAzemard NDucharme G(2015)Energy study for 28nm FDSOI technology2015 International Workshop on CMOS Variability (VARI)10.1109/VARI.2015.7456558(23-26)Online publication date: Sep-2015
https://doi.org/10.1109/VARI.2015.7456558
Kheirallah RGalliere JTodri-Sanial AAzemard NDucharme G(2015)Statistical energy study for 28nm FDSOI devices2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems10.1109/EuroSimE.2015.7103149(1-4)Online publication date: Apr-2015
https://doi.org/10.1109/EuroSimE.2015.7103149
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Index Terms

A probabilistic technique for full-chip leakage estimation
1. Hardware
  1. Hardware validation

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Published In

cover image ACM Conferences

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

August 2008

396 pages

ISBN:9781605581095

DOI:10.1145/1393921

General Chairs:
Vijaykrishnan Narayanan
Penn State University
,
C. P. Ravikumar
Texas Instruments
,
Joerg Henkel
Univeristy of Karlsruhe
,
Ali Keshavarzi
Intel Corporation
,
Program Chairs:
Vojin G. Oklobdzija
University of Texas at Dallas
,
Barry Pangrle
Pangrle Consulting

Copyright © 2008 ACM.

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Publication History

Published: 11 August 2008

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ISLPED08: International Symposium on Low Power Electronics and Design

August 11 - 13, 2008

Bangalore, India

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Kheirallah RGalliere JAzemard NDucharme G(2018)Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2018.8464159(88-91)Online publication date: Jul-2018
https://doi.org/10.1109/PATMOS.2018.8464159
Kheirallah RAzemard NDucharme G(2015)Energy study for 28nm FDSOI technology2015 International Workshop on CMOS Variability (VARI)10.1109/VARI.2015.7456558(23-26)Online publication date: Sep-2015
https://doi.org/10.1109/VARI.2015.7456558
Kheirallah RGalliere JTodri-Sanial AAzemard NDucharme G(2015)Statistical energy study for 28nm FDSOI devices2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems10.1109/EuroSimE.2015.7103149(1-4)Online publication date: Apr-2015
https://doi.org/10.1109/EuroSimE.2015.7103149
Liu SJingyi Zhang Qing Wu Qinru Qiu (2010)Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450547(390-398)Online publication date: Mar-2010
https://doi.org/10.1109/ISQED.2010.5450547
Liu SQiu MGao WTang XGuo B(2010)Hybrid of Job Sequencing and DVFS for Peak Temperature Reduction with Nondeterministic ApplicationsProceedings of the 2010 10th IEEE International Conference on Computer and Information Technology10.1109/CIT.2010.309(1780-1787)Online publication date: 29-Jun-2010
https://dl.acm.org/doi/10.1109/CIT.2010.309
Bhattacharjee AMartonosi M(2009)Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessorsACM SIGARCH Computer Architecture News10.1145/1555815.155579237:3(290-301)Online publication date: 20-Jun-2009
https://dl.acm.org/doi/10.1145/1555815.1555792
Bhattacharjee AMartonosi MKeckler SBarroso L(2009)Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessorsProceedings of the 36th annual international symposium on Computer architecture10.1145/1555754.1555792(290-301)Online publication date: 20-Jun-2009
https://dl.acm.org/doi/10.1145/1555754.1555792

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